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/kernel/linux/linux-5.10/drivers/clk/pistachio/
Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
[all …]
/kernel/linux/linux-5.10/drivers/memory/tegra/
Dtegra20.c12 .id = 0x00,
15 .id = 0x01,
18 .id = 0x02,
21 .id = 0x03,
24 .id = 0x04,
27 .id = 0x05,
30 .id = 0x06,
33 .id = 0x07,
36 .id = 0x08,
39 .id = 0x09,
[all …]
/kernel/linux/linux-5.10/drivers/clk/axs10x/
Di2s_pll_clock.c22 #define PLL_IDIV_REG 0x0
23 #define PLL_FBDIV_REG 0x4
24 #define PLL_ODIV0_REG 0x8
25 #define PLL_ODIV1_REG 0xC
37 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
38 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
39 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
40 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
41 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
42 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/marvell/mwifiex/
Dcfp.c40 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
42 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
43 0xb0, 0x48, 0x60, 0x6c, 0 };
45 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
46 0x0c, 0x12, 0x18, 0x24,
47 0x30, 0x48, 0x60, 0x6c, 0 };
49 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
50 0xb0, 0x48, 0x60, 0x6c, 0 };
51 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
52 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx8mp.c424 anatop_base = of_iomap(np, 0); in imx8mp_clocks_probe()
430 ccm_base = devm_platform_ioremap_resource(pdev, 0); in imx8mp_clocks_probe()
445 hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mp_clocks_probe()
453 …hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll… in imx8mp_clocks_probe()
454 …hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pl… in imx8mp_clocks_probe()
455 …hws[IMX8MP_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pl… in imx8mp_clocks_probe()
456 …hws[IMX8MP_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_re… in imx8mp_clocks_probe()
457 …hws[IMX8MP_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_… in imx8mp_clocks_probe()
458 …hws[IMX8MP_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_… in imx8mp_clocks_probe()
459 …hws[IMX8MP_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_… in imx8mp_clocks_probe()
[all …]
Dclk-imx8mn.c302 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
311 base = of_iomap(np, 0); in imx8mn_clocks_probe()
318 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
319 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
320 …hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
321 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
322 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
323 …hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
324 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
325 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
Dclk-imx8mm.c309 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
318 base = of_iomap(np, 0); in imx8mm_clocks_probe()
323 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
324 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
325 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
326 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
327 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
328 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
329 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
330 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dallwinner,sun8i-a83t-emac.yaml74 default: 0
75 minimum: 0
82 default: 0
83 minimum: 0
99 default: 0
100 minimum: 0
142 const: 0
151 "^ethernet-phy@[0-9a-f]$":
177 const: 0
194 reg = <0x01c0b000 0x104>;
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/bt8xx/
Dbt878.h21 #define BT878_VERSION_CODE 0x000000
23 #define BT878_AINT_STAT 0x100
24 #define BT878_ARISCS (0xf<<28)
37 #define BT878_AINT_MASK 0x104
39 #define BT878_AGPIO_DMA_CTL 0x10c
40 #define BT878_A_GAIN (0xf<<28)
47 #define BT878_DA_LRD (0x1f<<16)
52 #define BT878_DA_SDR (0xf<<8)
60 #define BT878_APACK_LEN 0x110
61 #define BT878_AFP_LEN (0xff<<16)
[all …]
/kernel/linux/linux-5.10/arch/mips/pci/
Dpci-vr41xx.h12 #define PCIU_BASE 0x0f000c00UL
13 #define PCIU_SIZE 0x200UL
15 #define PCIMMAW1REG 0x00
16 #define PCIMMAW2REG 0x04
17 #define PCITAW1REG 0x08
18 #define PCITAW2REG 0x0c
19 #define PCIMIOAWREG 0x10
20 #define IBA(addr) ((addr) & 0xff000000U)
21 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
22 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dberlin-usb-phy.txt6 - #phys-cells: should be 0
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
/kernel/linux/linux-5.10/arch/arm/mach-tango/
Dsmc.h4 #define tango_set_l2_control(val) tango_smc(val, 0x102)
5 #define tango_start_aux_core(val) tango_smc(val, 0x104)
6 #define tango_set_aux_boot_addr(val) tango_smc(val, 0x105)
7 #define tango_suspend(val) tango_smc(val, 0x120)
8 #define tango_aux_core_die(val) tango_smc(val, 0x121)
9 #define tango_aux_core_kill(val) tango_smc(val, 0x122)
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/d71/
Dd71_regs.h11 #define BLK_BLOCK_INFO 0x000
12 #define BLK_PIPELINE_INFO 0x004
13 #define BLK_MAX_LINE_SIZE 0x008
14 #define BLK_VALID_INPUT_ID0 0x020
15 #define BLK_OUTPUT_ID0 0x060
16 #define BLK_INPUT_ID0 0x080
17 #define BLK_IRQ_RAW_STATUS 0x0A0
18 #define BLK_IRQ_CLEAR 0x0A4
19 #define BLK_IRQ_MASK 0x0A8
20 #define BLK_IRQ_STATUS 0x0AC
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-orion5x/
Dbridge-regs.h14 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
16 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
18 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
19 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
21 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
23 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
25 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
27 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
29 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
31 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dregs-sys-s3c64xx.h16 #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
17 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
18 #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
20 #define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
22 #define S3C64XX_OTHERS S3C_SYSREG(0x900)
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/
Dberlin,reset.txt22 resets = <&chip_rst 0x104 12>;
/kernel/linux/linux-5.10/include/linux/
Dmicrel_phy.h11 #define MICREL_PHY_ID_MASK 0x00fffff0
13 #define PHY_ID_KSZ8873MLL 0x000e7237
14 #define PHY_ID_KSZ9021 0x00221610
15 #define PHY_ID_KSZ9021RLRN 0x00221611
16 #define PHY_ID_KS8737 0x00221720
17 #define PHY_ID_KSZ8021 0x00221555
18 #define PHY_ID_KSZ8031 0x00221556
19 #define PHY_ID_KSZ8041 0x00221510
21 #define PHY_ID_KSZ8041RNLI 0x00221537
22 #define PHY_ID_KSZ8051 0x00221550
[all …]
Datmel_pdc.h15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Decx-common.dtsi14 cpu_suspend = <0x84000002>;
15 cpu_off = <0x84000004>;
16 cpu_on = <0x84000006>;
27 reg = <0xffe08000 0x10000>;
28 interrupts = <0 83 4>;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
35 calxeda,led-order = <4 0 1 2 3>;
40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>;
48 reg = <0xfff20000 0x1000>;
[all …]
/kernel/linux/linux-5.10/drivers/media/usb/gspca/
Dstk1135.h8 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
9 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
10 #define STK1135_REG_IDATA 0x008 /* Interrupt data */
11 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
12 #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */
14 #define STK1135_REG_SENSO 0x018 /* Sensor select options */
15 #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */
17 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
19 #define STK1135_REG_CISPO 0x110 /* Capture image starting position */
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/kernel/linux/linux-5.10/drivers/media/rc/keymaps/
Drc-x96max.c13 { 0x140, KEY_POWER },
22 { 0x118, KEY_VOLUMEUP },
23 { 0x110, KEY_VOLUMEDOWN },
25 { 0x143, KEY_MUTE }, // config
27 { 0x100, KEY_EPG }, // mouse
28 { 0x119, KEY_BACK },
30 { 0x116, KEY_UP },
31 { 0x151, KEY_LEFT },
32 { 0x150, KEY_RIGHT },
33 { 0x11a, KEY_DOWN },
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dcalxeda.yaml20 const: 0
47 reg = <0x3fffc000 0x1000>;
51 #size-cells = <0>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
63 reg = <0x108>;
67 #clock-cells = <0>;
70 reg = <0x100>;
74 #clock-cells = <0>;
77 reg = <0x104>;
/kernel/linux/linux-5.10/arch/powerpc/platforms/82xx/
Dpq2.c21 #define RMR_CSRE 0x00000001
30 in_8(&cpm2_immr->im_clkrst.res[0]); in pq2_restart()
40 if (bus == 0 && PCI_SLOT(devfn) == 0) in NOKPROBE_SYMBOL()
51 if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b) in pq2_pci_add_bridge()
62 setup_indirect_pci(hose, r.start + 0x100, r.start + 0x104, 0); in pq2_pci_add_bridge()

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