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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_1_3_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f
32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0
33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780
34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7
35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800
36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb
[all …]
Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_2_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
Dsmu_7_0_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dpasemi_nand.c26 #define LBICTRL_LPCCTL_NR 0x00004000
37 while (len > 0x800) { in pasemi_read_buf()
38 memcpy_fromio(buf, chip->legacy.IO_ADDR_R, 0x800); in pasemi_read_buf()
39 buf += 0x800; in pasemi_read_buf()
40 len -= 0x800; in pasemi_read_buf()
48 while (len > 0x800) { in pasemi_write_buf()
49 memcpy_toio(chip->legacy.IO_ADDR_R, buf, 0x800); in pasemi_write_buf()
50 buf += 0x800; in pasemi_write_buf()
51 len -= 0x800; in pasemi_write_buf()
83 return 0; in pasemi_attach_chip()
[all …]
Dcs553x_nand.c11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12 * where 0-3 reflects the chip select for NAND.
30 #define MSR_DIVIL_GLD_CAP 0x51400000 /* DIVIL capabilitiies */
31 #define CAP_CS5535 0x2df000ULL
32 #define CAP_CS5536 0x5df500ULL
35 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */
37 #define MSR_NANDF_RSVD 0x5140001d /* Reserved */
40 #define MSR_DIVIL_LBAR_FLSH0 0x51400010 /* Flash Chip Select 0 */
41 #define MSR_DIVIL_LBAR_FLSH1 0x51400011 /* Flash Chip Select 1 */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf119.c45 mask[head->id] = nvkm_rd32(device, 0x6101d4 + (head->id * 0x800)); in gf119_disp_super()
49 if (disp->super & 0x00000001) { in gf119_disp_super()
50 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); in gf119_disp_super()
53 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
58 if (disp->super & 0x00000002) { in gf119_disp_super()
60 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
66 if (!(mask[head->id] & 0x00010000)) in gf119_disp_super()
71 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
76 if (disp->super & 0x00000004) { in gf119_disp_super()
78 if (!(mask[head->id] & 0x00001000)) in gf119_disp_super()
[all …]
/kernel/linux/linux-5.10/arch/riscv/kernel/
Dmodule.c24 return 0; in apply_r_riscv_32_rela()
30 return 0; in apply_r_riscv_64_rela()
37 u32 imm12 = (offset & 0x1000) << (31 - 12); in apply_r_riscv_branch_rela()
38 u32 imm11 = (offset & 0x800) >> (11 - 7); in apply_r_riscv_branch_rela()
39 u32 imm10_5 = (offset & 0x7e0) << (30 - 10); in apply_r_riscv_branch_rela()
40 u32 imm4_1 = (offset & 0x1e) << (11 - 4); in apply_r_riscv_branch_rela()
42 *location = (*location & 0x1fff07f) | imm12 | imm11 | imm10_5 | imm4_1; in apply_r_riscv_branch_rela()
43 return 0; in apply_r_riscv_branch_rela()
50 u32 imm20 = (offset & 0x100000) << (31 - 20); in apply_r_riscv_jal_rela()
51 u32 imm19_12 = (offset & 0xff000); in apply_r_riscv_jal_rela()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
Dnouveau_reg.h3 #define NV04_PFB_BOOT_0 0x00100000
4 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
6 # define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
7 # define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
8 # define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
9 # define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
10 # define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
11 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
12 # define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
[all …]
/kernel/linux/linux-5.10/arch/sh/include/cpu-sh4a/cpu/
Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/
Dmediatek-vcodec.txt32 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
33 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
34 <0 0x16021000 0 0x800>, /*VDEC_LD*/
35 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
36 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
37 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
38 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
39 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
40 <0 0x16026800 0 0x800>, /*VP8_VD*/
41 <0 0x16027000 0 0x800>, /*VP6_VD*/
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h11 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
13 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
14 /* 3. RF register 0x00-2E */
19 /* 3. Page8(0x800) */
20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
21 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
23 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
24 #define rFPGA0_XA_HSSIParameter2 0x824
25 #define rFPGA0_XB_HSSIParameter1 0x828
26 #define rFPGA0_XB_HSSIParameter2 0x82c
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt37 0 and 1 (in this order).
55 reg = <0x48058000 0x1000>,
56 <0x48059000 0x1000>;
77 reg = <0x4805a000 0x800>,
78 <0x4805a800 0x800>;
92 reg = <0x4805b000 0x800>,
93 <0x4805b800 0x800>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsam9x60.dtsi36 #size-cells = <0>;
38 cpu@0 {
41 reg = <0>;
47 reg = <0x20000000 0x10000000>;
53 #clock-cells = <0>;
58 #clock-cells = <0>;
64 reg = <0x00300000 0x100000>;
67 ranges = <0 0x00300000 0x100000>;
78 #size-cells = <0>;
80 reg = <0x00500000 0x100000
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgk20a.c29 nvkm_mask(device, 0x137250, 0x3f, 0); in gk20a_ibus_init_ibus_ring()
31 nvkm_mask(device, 0x000200, 0x20, 0); in gk20a_ibus_init_ibus_ring()
33 nvkm_mask(device, 0x000200, 0x20, 0x20); in gk20a_ibus_init_ibus_ring()
35 nvkm_wr32(device, 0x12004c, 0x4); in gk20a_ibus_init_ibus_ring()
36 nvkm_wr32(device, 0x122204, 0x2); in gk20a_ibus_init_ibus_ring()
37 nvkm_rd32(device, 0x122204); in gk20a_ibus_init_ibus_ring()
43 nvkm_wr32(device, 0x122354, 0x800); in gk20a_ibus_init_ibus_ring()
44 nvkm_wr32(device, 0x128328, 0x800); in gk20a_ibus_init_ibus_ring()
45 nvkm_wr32(device, 0x124320, 0x800); in gk20a_ibus_init_ibus_ring()
52 u32 status0 = nvkm_rd32(device, 0x120058); in gk20a_ibus_intr()
[all …]
/kernel/linux/linux-5.10/arch/m68k/mac/
Dmacboing.c23 static __u8 mac_asc_wave_tab[ 0x800 ];
26 * Alan's original sine table; needs interpolating to 0x800
27 * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
30 0, 39, 75, 103, 121, 127, 121, 103, 75, 39,
31 0, -39, -75, -103, -121, -127, -121, -103, -75, -39
37 static volatile __u8* mac_asc_regs = ( void* )0x50F14000;
44 static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
74 * mac_asc_regs[ 0x800 ] & 0xF0 != 0 in mac_init_asc()
84 mac_asc_regs = ( void* )0x50010000; in mac_init_asc()
147 for ( i = 0; i < 0x400; i++ ) in mac_init_asc()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.yaml43 0: Global Timer Interrupt 0
47 4: Local Timer Interrupt 0
78 reg = <0x10050000 0x800>;
98 reg = <0x101C0000 0x800>;
119 reg = <0x10050000 0x800>;
139 reg = <0x10050000 0x800>;
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dmac_asc.h13 #define ASC_BUF_BASE 0x00 /* RAM buffer offset */
14 #define ASC_BUF_SIZE 0x800
16 #define ASC_CONTROL 0x800
17 #define ASC_CONTROL_OFF 0x00
18 #define ASC_FREQ(chan,byte) ((0x810)+((chan)<<3)+(byte))
19 #define ASC_ENABLE 0x801
20 #define ASC_ENABLE_SAMPLE 0x02
21 #define ASC_MODE 0x802
22 #define ASC_MODE_SAMPLE 0x02
24 #define ASC_VOLUME 0x806
[all …]
/kernel/linux/linux-5.10/drivers/net/arcnet/
Darc-rimi.c73 dev->dev_addr[0], dev->mem_start, dev->irq); in arcrimi_probe()
76 if (dev->mem_start <= 0 || dev->irq <= 0) { in arcrimi_probe()
81 if (dev->dev_addr[0] == 0) { in arcrimi_probe()
112 res = 0; in check_mirror()
139 if (request_irq(dev->irq, arcnet_interrupt, 0, "arcnet (RIM I)", dev)) { in arcrimi_found()
159 check_mirror(shmem - MIRROR_SIZE, MIRROR_SIZE) == 0 && in arcrimi_found()
210 dev->dev_addr[0] = arcnet_readb(lp->mem_start, COM9026_REG_R_STATION); in arcrimi_found()
213 dev->dev_addr[0], in arcrimi_found()
222 return 0; in arcrimi_found()
243 void __iomem *ioaddr = lp->mem_start + 0x800; in arcrimi_reset()
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmpc7448hpc2.dts29 #size-cells =<0>;
31 PowerPC,7448@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K bytes
37 i-cache-size = <0x8000>; // L1, 32K bytes
38 timebase-frequency = <0>; // 33 MHz, from uboot
39 clock-frequency = <0>; // From U-Boot
40 bus-frequency = <0>; // From U-Boot
46 reg = <0x0 0x20000000 // DDR2 512M at 0
54 ranges = <0x0 0xc0000000 0x10000>;
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Dmv88e1xxx.h7 # define BMCR_SPEED1000 0x40
11 # define ADVERTISE_PAUSE 0x400
14 # define ADVERTISE_PAUSE_ASYM 0x800
22 #define GBCR_ADV_1000HALF 0x100
23 #define GBCR_ADV_1000FULL 0x200
24 #define GBCR_PREFER_MASTER 0x400
25 #define GBCR_MANUAL_AS_MASTER 0x800
26 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000
29 #define GBSR_LP_1000HALF 0x400
30 #define GBSR_LP_1000FULL 0x800
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/
Da6xx_gpu_state.h13 0x8000, 0x8006, 0x8010, 0x8092, 0x8094, 0x809d, 0x80a0, 0x80a6,
14 0x80af, 0x80f1, 0x8100, 0x8107, 0x8109, 0x8109, 0x8110, 0x8110,
15 0x8400, 0x840b,
19 0x8800, 0x8806, 0x8809, 0x8811, 0x8818, 0x881e, 0x8820, 0x8865,
20 0x8870, 0x8879, 0x8880, 0x8889, 0x8890, 0x8891, 0x8898, 0x8898,
21 0x88c0, 0x88c1, 0x88d0, 0x88e3, 0x8900, 0x890c, 0x890f, 0x891a,
22 0x8c00, 0x8c01, 0x8c08, 0x8c10, 0x8c17, 0x8c1f, 0x8c26, 0x8c33,
26 0x88f0, 0x88f3, 0x890d, 0x890e, 0x8927, 0x8928, 0x8bf0, 0x8bf1,
27 0x8c02, 0x8c07, 0x8c11, 0x8c16, 0x8c20, 0x8c25,
31 0x9200, 0x9216, 0x9218, 0x9236, 0x9300, 0x9306,
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/kernel/linux/linux-5.10/arch/arm64/include/asm/
Dbrk-imm.h11 * 0x004: for installing kprobes
12 * 0x005: for installing uprobes
13 * 0x006: for kprobe software single-step
14 * Allowed values for kgdb are 0x400 - 0x7ff
15 * 0x100: for triggering a fault on purpose (reserved)
16 * 0x400: for dynamic BRK instruction
17 * 0x401: for compile time BRK instruction
18 * 0x800: kernel-mode BUG() and WARN() traps
19 * 0x9xx: tag-based KASAN trap (allowed values 0x900 - 0x9ff)
21 #define KPROBES_BRK_IMM 0x004
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