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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/
Damlogic,meson-saradc.yaml129 reg = <0x0 0x8680 0x0 0x34>;
140 reg = <0x0 0x9680 0x0 0x34>;
/kernel/linux/linux-5.10/include/video/
Dpermedia2.h17 #define PM2_REGS_SIZE 0x10000
19 #define PM2TAG(r) (u32 )(((r)-0x8000)>>3)
25 #define PM2R_RESET_STATUS 0x0000
26 #define PM2R_IN_FIFO_SPACE 0x0018
27 #define PM2R_OUT_FIFO_WORDS 0x0020
28 #define PM2R_APERTURE_ONE 0x0050
29 #define PM2R_APERTURE_TWO 0x0058
30 #define PM2R_FIFO_DISCON 0x0068
31 #define PM2R_CHIP_CONFIG 0x0070
33 #define PM2R_REBOOT 0x1000
[all …]
Dpm3fb.h19 #define PM3ResetStatus 0x0000
20 #define PM3IntEnable 0x0008
21 #define PM3IntFlags 0x0010
22 #define PM3InFIFOSpace 0x0018
23 #define PM3OutFIFOWords 0x0020
24 #define PM3DMAAddress 0x0028
25 #define PM3DMACount 0x0030
26 #define PM3ErrorFlags 0x0038
27 #define PM3VClkCtl 0x0040
28 #define PM3TestRegister 0x0048
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dmeson.dtsi22 reg = <0xc1100000 0x200000>;
25 ranges = <0x0 0xc1100000 0x200000>;
31 reg = <0x4000 0x400>;
36 reg = <0x7c00 0x200>;
41 reg = <0x8100 0x8>;
46 reg = <0x84c0 0x18>;
53 reg = <0x84dc 0x18>;
60 reg = <0x8500 0x20>;
63 #size-cells = <0>;
69 reg = <0x8550 0x10>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/
Dmeson-gx.dtsi29 hwrom_reserved: hwrom@0 {
30 reg = <0x0 0x0 0x0 0x1000000>;
36 reg = <0x0 0x10000000 0x0 0x200000>;
42 reg = <0x0 0x05000000 0x0 0x300000>;
49 size = <0x0 0x10000000>;
50 alignment = <0x0 0x400000>;
78 #address-cells = <0x2>;
79 #size-cells = <0x0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dnid.h33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
[all …]
Dcikd.h27 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
34 #define DIDT_SQ_CTRL0 0x0
35 # define DIDT_CTRL_EN (1 << 0)
36 #define DIDT_DB_CTRL0 0x20
37 #define DIDT_TD_CTRL0 0x40
38 #define DIDT_TCP_CTRL0 0x60
41 #define DPM_TABLE_475 0x3F768
42 # define SamuBootLevel(x) ((x) << 0)
43 # define SamuBootLevel_MASK 0x000000ff
[all …]
Devergreend.h33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
40 #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003
41 #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003
42 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
43 #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002
44 #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002
45 #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002
[all …]
Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath5k/
Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/kernel/linux/linux-5.10/sound/pci/hda/
Dpatch_realtek.c141 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in alc_read_coefex_idx()
142 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, 0); in alc_read_coefex_idx()
147 alc_read_coefex_idx(codec, 0x20, coef_idx)
152 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in alc_write_coefex_idx()
153 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PROC_COEF, coef_val); in alc_write_coefex_idx()
157 alc_write_coefex_idx(codec, 0x20, coef_idx, coef_val)
171 alc_update_coefex_idx(codec, 0x20, coef_idx, mask, bits_set)
173 /* a special bypass for COEF 0; read the cached value at the second time */
179 spec->coef0 = alc_read_coef_idx(codec, 0); in alc_get_coef0()
194 #define WRITE_COEF(_idx, _val) WRITE_COEFEX(0x20, _idx, _val)
[all …]
/kernel/linux/linux-5.10/fs/nls/
Dnls_cp936.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x4E02,0x4E04,0x4E05,0x4E06,0x4E0F,0x4E12,0x4E17,0x4E1F,/* 0x40-0x47 */
26 0x4E20,0x4E21,0x4E23,0x4E26,0x4E29,0x4E2E,0x4E2F,0x4E31,/* 0x48-0x4F */
[all …]