| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
169 "brcm,brcmstb-ddr-phy-v71.1"
170 "brcm,brcmstb-ddr-phy-v72.0"
171 "brcm,brcmstb-ddr-phy-v225.1"
172 "brcm,brcmstb-ddr-phy-v240.1"
173 "brcm,brcmstb-ddr-phy-v240.2"
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
75 memc-ddr@2000 {
79 ddr-phy@6000 {
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
92 "brcm,brcmstb-ddr-phy-v64.5"
93 "brcm,brcmstb-ddr-phy"
95 - reg : the DDR PHY register range and length
99 ddr-phy@6000 {
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
10 - compatible: has to be "qca,<soc-type>-ddr-controller",
11 "qca,[ar7100|ar7240]-ddr-controller" as fallback.
12 On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
13 fallback, otherwise "qca,ar7240-ddr-controller" should be used.
15 - #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
21 compatible = "qca,ar9132-ddr-controller",
22 "qca,ar7240-ddr-controller";
[all …]
|
| D | calxeda-ddr-ctrlr.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller binding
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
|
| D | synopsys.txt | 3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16 - reg: Should contain DDR controller registers location and length.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/perf/ |
| D | fsl-imx-ddr.yaml | 4 $id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
7 title: Freescale(NXP) IMX8 DDR performance monitor
16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mp-ddr-pmu
21 - fsl,imx8mm-ddr-pmu
22 - fsl,imx8mn-ddr-pmu
23 - fsl,imx8mq-ddr-pmu
24 - fsl,imx8mp-ddr-pmu
25 - const: fsl,imx8m-ddr-pmu
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | qca,ath79-cpu-intc.txt | 3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
43 #qca,ddr-wb-channel-cells = <1>;
|
| /kernel/linux/linux-5.10/arch/mips/include/asm/mach-rc32434/ |
| D | ddr.h | 2 * Definitions for the DDR registers
34 /* DDR register structure */
51 /* DDR banks masks */
56 /* DDR bank0 registers */
86 /* DDR bank C registers */
91 /* Custom DDR bank registers */
102 /* DDR QSC registers */
114 /* DDR LLC registers */
126 /* DDR LLFC registers */
132 /* DDR DLLTA registers */
[all …]
|
| /kernel/linux/linux-5.10/include/linux/ |
| D | fsl-diu-fb.h | 65 * These are the fields of area descriptor(in DDR memory) for every plane
68 /* Word 0(32-bit) in DDR memory */
81 /* Word 1(32-bit) in DDR memory */
84 /* Word 2(32-bit) in DDR memory */
92 /* Word 3(32-bit) in DDR memory */
100 /* Word 4(32-bit) in DDR memory */
108 /* Word 5(32-bit) in DDR memory */
116 /* Word 6(32-bit) in DDR memory */
122 /* Word 7(32-bit) in DDR memory */
129 /* Word 8(32-bit) in DDR memory */
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm7445.dtsi | 239 memc-ddr@2000 {
240 compatible = "brcm,brcmstb-memc-ddr";
244 ddr-phy@6000 {
245 compatible = "brcm,brcmstb-ddr-phy-v240.1";
250 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
261 memc-ddr@2000 {
262 compatible = "brcm,brcmstb-memc-ddr";
266 ddr-phy@6000 {
267 compatible = "brcm,brcmstb-ddr-phy-v240.1";
272 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/rb532/ |
| D | prom.c | 22 #include <asm/mach-rc32434/ddr.h>
30 .name = "ddr-reg",
109 struct ddr_ram __iomem *ddr; in prom_init() local
113 ddr = ioremap(ddr_reg[0].start, in prom_init()
116 if (!ddr) { in prom_init()
117 printk(KERN_ERR "Unable to remap DDR register\n"); in prom_init()
121 ddrbase = (phys_addr_t)&ddr->ddrbase; in prom_init()
122 memsize = (phys_addr_t)&ddr->ddrmask; in prom_init()
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | amlogic,meson8-ddr-clkc.yaml | 4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml#
7 title: Amlogic DDR Clock Controller Device Tree Bindings
15 - amlogic,meson8-ddr-clkc
16 - amlogic,meson8b-ddr-clkc
43 compatible = "amlogic,meson8-ddr-clkc";
|
| D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
|
| /kernel/linux/linux-5.10/drivers/memory/ |
| D | Kconfig | 11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
34 bool "Atmel (Multi-port DDR-)SDRAM Controller"
40 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
41 Starting with the at91sam9g45, this controller supports SDR, DDR and
42 LP-DDR memories.
63 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
95 select DDR
|
| D | of_memory.c | 19 * of_get_min_tck() - extract min timing values for ddr
20 * @np: pointer to ddr device tree node
92 * of_get_ddr_timings() - extracts the ddr timings and updates no of
94 * @np_ddr: Pointer to ddr device tree node
95 * @dev: Device requesting for ddr timings
96 * @device_type: Type of ddr(LPDDR2 S2/S4)
97 * @nr_frequencies: No of frequencies available for ddr
157 * @np: pointer to ddr device tree node
243 * @np_ddr: Pointer to ddr device tree node
244 * @dev: Device requesting for ddr timings
[all …]
|
| /kernel/linux/linux-5.10/drivers/soc/bcm/brcmstb/pm/ |
| D | pm-arm.c | 6 * S3: power off all of the chip except the Always ON (AON) island; keep DDR is
8 * S5: (a.k.a. S3 cold boot) much like S3, except DDR is powered down, so we
368 * from SRAM, in order to allow DDR to come back up safely before we continue.
579 .compatible = "brcm,brcmstb-ddr-phy-v71.1",
583 .compatible = "brcm,brcmstb-ddr-phy-v72.0",
587 .compatible = "brcm,brcmstb-ddr-phy-v225.1",
591 .compatible = "brcm,brcmstb-ddr-phy-v240.1",
596 .compatible = "brcm,brcmstb-ddr-phy-v240.2",
617 { .compatible = "brcm,brcmstb-ddr-shimphy-v1.0" },
623 .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/pci/tw5864/ |
| D | tw5864-reg.h | 17 /* DDR controller enabled */
30 * Video Frame mapping in DDR
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
145 /* DDR Single Access Page Number */
147 /* DDR-DPR Burst Read Enable */
150 * DDR A/B Select as HOST access
156 * DDR Access Mode Select
157 * 0 Single R/W Access (Host <-> DDR)
287 /* DDR base address of OSD rectangle attribute data */
[all …]
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-ath79-cpu.c | 27 * This array map the interrupt lines to the DDR write buffer channels.
63 node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells"); in ar79_cpu_intc_of_init()
70 node, "qca,ddr-wb-channel-interrupts", i, &irq); in ar79_cpu_intc_of_init()
75 node, "qca,ddr-wb-channels", in ar79_cpu_intc_of_init()
76 "#qca,ddr-wb-channel-cells", in ar79_cpu_intc_of_init()
|
| /kernel/linux/linux-5.10/include/memory/ |
| D | renesas-rpc-if.h | 25 bool ddr; member
31 bool ddr; member
43 bool ddr; member
51 bool ddr; member
76 u32 ddr; /* DRDRENR or SMDRENR */ member
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/knightslanding/ |
| D | memory.json | 950 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
953 …nd cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
961 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
964 …ption": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
972 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
975 …ts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
983 "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
986 … prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
994 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
997 …"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and …
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 5 - devfreq-events: Node to get DDR loading, Refer to
19 It should be a DCF interrupt. When DDR DVFS finishes
24 Following properties relate to DDR timing:
26 - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
63 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
68 MHz (Mega Hz). When DDR frequency is less than
74 when the DDR frequency is less then ddr3_odt_dis_freq,
101 When DDR frequency is less then ddr3_odt_dis_freq,
129 MHz (Mega Hz). When the DDR frequency is less then
|
| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-driver-bd9571mwv-regulator | 5 Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
10 A. With a momentary power switch (or pulse signal), DDR
26 DDR Backup Mode must be explicitly enabled by the user,
|
| /kernel/linux/linux-5.10/arch/mips/boot/dts/qca/ |
| D | ar9132.dtsi | 28 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
29 qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
52 compatible = "qca,ar9132-ddr-controller",
53 "qca,ar7240-ddr-controller";
56 #qca,ddr-wb-channel-cells = <1>;
98 clock-output-names = "cpu", "ddr", "ahb";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-msm.txt | 50 - qcom,ddr-config: Certain chipsets and platforms require particular settings
64 1. Data path : sdhc to ddr
67 is "sdhc-ddr" and for config interconnect path it is
91 interconnect-names = "sdhc-ddr","cpu-sdhc";
94 qcom,ddr-config = <0x80040868>;
114 qcom,ddr-config = <0x80040868>;
|
| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | meson8-ddr.c | 3 * Amlogic Meson8 DDR clock controller
8 #include <dt-bindings/clock/meson8-ddr-clkc.h>
136 { .compatible = "amlogic,meson8-ddr-clkc" },
137 { .compatible = "amlogic,meson8b-ddr-clkc" },
144 .name = "meson8-ddr-clkc",
|