/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
D | samsung,s3c2412-clock.txt | 47 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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D | samsung,s3c2410-clock.txt | 48 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>;
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D | samsung,s3c2443-clock.txt | 53 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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D | samsung,s3c64xx-clock.txt | 74 clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
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D | rockchip,rk3308-cru.txt | 55 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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D | rockchip,rk3399-cru.txt | 63 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
D | samsung_uart.yaml | 123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | s3c2416.dtsi | 100 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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D | s3c64xx.dtsi | 123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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/kernel/linux/linux-5.10/drivers/clk/samsung/ |
D | clk-s3c2410.c | 86 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0), 177 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"), 180 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"), 265 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"), 268 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
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D | clk-s3c2412.c | 115 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0), 137 ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"), 140 ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
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D | clk-s3c2443.c | 142 GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0), 152 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"), 156 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
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D | clk-s3c64xx.c | 244 GATE_BUS(PCLK_UART0, "pclk_uart0", "pclk", PCLK_GATE, 1), 349 ALIAS(PCLK_UART0, "s3c6400-uart.0", "uart"),
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/kernel/linux/linux-5.10/include/dt-bindings/clock/ |
D | s3c2410.h | 31 #define PCLK_UART0 16 macro
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D | s3c2412.h | 50 #define PCLK_UART0 41 macro
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D | s3c2443.h | 68 #define PCLK_UART0 72 macro
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D | rk3036-cru.h | 68 #define PCLK_UART0 341 macro
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D | samsung,s3c64xx-clock.h | 88 #define PCLK_UART0 73 macro
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D | exynos7-clk.h | 78 #define PCLK_UART0 1 macro
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D | rk3188-cru-common.h | 84 #define PCLK_UART0 332 macro
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D | rk3228-cru.h | 107 #define PCLK_UART0 341 macro
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D | rk3128-cru.h | 108 #define PCLK_UART0 341 macro
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D | rv1108-cru.h | 116 #define PCLK_UART0 265 macro
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D | rk3288-cru.h | 133 #define PCLK_UART0 341 macro
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/kernel/linux/linux-5.10/drivers/clk/rockchip/ |
D | clk-rk3188.c | 650 GATE(PCLK_UART0, "pclk_uart0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS), 740 GATE(PCLK_UART0, "pclk_uart0", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 0, GFLAGS),
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