| /kernel/linux/linux-5.10/drivers/clk/baikal-t1/ |
| D | clk-ccu-pll.c | 54 * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
56 * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
58 * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
60 * all the devices consuming those PLLs, they will be marked as critical too.
78 struct ccu_pll *plls[CCU_PLL_NUM]; member
88 pll = data->plls[idx]; in ccu_pll_find_desc()
159 data->plls[idx] = ccu_pll_hw_register(&init); in ccu_pll_clk_register()
160 if (IS_ERR(data->plls[idx])) { in ccu_pll_clk_register()
161 ret = PTR_ERR(data->plls[idx]); in ccu_pll_clk_register()
179 ccu_pll_hw_unregister(data->plls[idx]); in ccu_pll_clk_register()
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| D | Kconfig | 11 in them are fed with clocks generated by a hierarchy of PLLs,
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
23 System Controller. These are five PLLs placed at the root of the
37 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-pll.yaml | 19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
22 in general can provide any frequency supported by the CCU PLLs).
23 2) PLLs clocks generators (PLLs) - described in this binding file.
31 | +-|PLLs|------|- DDR controller
47 output is primarily connected to a set of CCU PLLs. There are five PLLs
51 peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
53 the PLL configuration procedure. The PLLs work as depicted on the next
77 The PLLs CLKOUT is then either directly connected with the corresponding
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| D | baikal,bt1-ccu-div.yaml | 19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
24 in general can provide any frequency supported by the CCU PLLs).
25 2) PLLs clocks generators (PLLs).
34 | +-|PLLs|------|- DDR controller
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
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| D | brcm,bcm2835-cprman.txt | 7 of the BCM2835. There is a level of PLLs deriving from an external
9 few PLLs, and a level of mostly-generic clock generators sourcing from
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| D | st,nomadik.txt | 7 PLLs and clock gates.
23 PLL nodes: these nodes represent the two PLLs on the system,
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| D | marvell,berlin.txt | 9 (BG2, BG2CD, BG2Q) SoCs share the same IP for PLLs and clocks, with some
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc.h | 46 * Some PLLs require the PLL SW override bit to be set before changes can be
52 * Some PLLs use a different way to control clock power, via the PWRDWN bit in
58 * Some PLLs have separate registers for Status and Control. Identify this to
64 * Some PLLs have an additional divide by 2 in master clock calculation;
71 * Some PLLs provide a look up table for the leaf clock frequencies and
79 * Some PLLs have an active low reset
191 * Main clock control parameters for clocks derived from the PLLs
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| /kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/ |
| D | pll.c | 32 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_register()
33 if (!dss->plls[i]) { in dss_pll_register()
34 dss->plls[i] = pll; in dss_pll_register()
48 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_unregister()
49 if (dss->plls[i] == pll) { in dss_pll_unregister()
50 dss->plls[i] = NULL; in dss_pll_unregister()
61 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) { in dss_pll_find()
62 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0) in dss_pll_find()
63 return dss->plls[i]; in dss_pll_find()
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| D | dss.h | 126 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
127 * Type-B PLLs: clkout[0] refers to m2.
255 struct dss_pll *plls[4]; member
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| /kernel/linux/linux-5.10/arch/arm/mach-ep93xx/ |
| D | hardware.h | 14 * loops (PLLs) to multiply the incoming external clock signal to much
16 * to produce the needed clocks. The PLLs operate independently of one
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| /kernel/linux/linux-5.10/sound/soc/uniphier/ |
| D | aio-cpu.c | 32 return chip->plls[pll_id].enable; in is_valid_pll()
138 pll = &aio->chip->plls[pll_id]; in find_divider()
663 chip->plls = devm_kcalloc(dev, in uniphier_aio_probe()
667 if (!chip->plls) in uniphier_aio_probe()
669 memcpy(chip->plls, chip->chip_spec->plls, in uniphier_aio_probe()
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-s3c2410.c | 33 /* list of PLLs to be registered */
346 /* Register PLLs. */ in s3c2410_common_clk_init()
353 * plls follow different calculation schemes, with the in s3c2410_common_clk_init()
354 * upll following the same scheme as the s3c2410 plls in s3c2410_common_clk_init()
362 /* Register PLLs. */ in s3c2410_common_clk_init()
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | s3c24xx-cpufreq.c | 620 * @plls: The list of PLL entries.
621 * @plls_no: The size of the PLL entries @plls.
623 * Register the given set of PLLs with the system.
625 int s3c_plltab_register(struct cpufreq_frequency_table *plls, in s3c_plltab_register() argument
635 memcpy(vals, plls, size); in s3c_plltab_register()
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | Kconfig | 55 This driver supports the HSDK core, system, ddr, tunnel and hdmi PLLs
175 synthesizer. Each chip has different number of PLLs and outputs.
176 For example, the CDCE925 contains two PLLs with spread-spectrum
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| /kernel/linux/linux-5.10/arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 252 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
257 * start by switching to CLKM to safely disable PLLs, then switch to
267 /* 2uS delay delay between changing SCLK and disabling PLLs */
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| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu_sdm.c | 77 * some PLLs support this. On later SoCs, all PLLs support this.
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | oxsemi,ox820.h | 9 /* PLLs */
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| D | jz4740-cgu.h | 7 * - PLLs
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| D | marvell,pxa910.h | 5 /* fixed clocks and plls */
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| D | x1000-cgu.h | 7 * - PLLs
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| D | clk-pll.c | 32 * MediaTek PLLs are configured through their pcw value. The pcw value describes
345 const struct mtk_pll_data *plls, int num_plls, struct clk_onecell_data *clk_data) in mtk_clk_register_plls() argument
358 const struct mtk_pll_data *pll = &plls[i]; in mtk_clk_register_plls()
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | dra62x-clocks.dtsi | 5 /* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */
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| /kernel/linux/linux-5.10/drivers/clk/keystone/ |
| D | Kconfig | 7 a power sleep control module that gate the clock to the IPs and PLLs.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,apmixedsys.txt | 4 The Mediatek apmixedsys controller provides the PLLs to the system.
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