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/kernel/linux/linux-5.10/drivers/watchdog/
Dsama5d4_wdt.c52 #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
54 #define wdt_read(wdt, field) \ argument
55 readl_relaxed((wdt)->reg_base + (field))
60 static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val) in wdt_write() argument
67 while (time_before(jiffies, wdt->last_ping + WDT_DELAY)) in wdt_write()
69 writel_relaxed(val, wdt->reg_base + field); in wdt_write()
70 wdt->last_ping = jiffies; in wdt_write()
73 static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val) in wdt_write_nosleep() argument
75 if (time_before(jiffies, wdt->last_ping + WDT_DELAY)) in wdt_write_nosleep()
77 writel_relaxed(val, wdt->reg_base + field); in wdt_write_nosleep()
[all …]
Dsprd_wdt.c83 struct sprd_wdt *wdt = (struct sprd_wdt *)dev_id; in sprd_wdt_isr() local
85 sprd_wdt_unlock(wdt->base); in sprd_wdt_isr()
86 writel_relaxed(SPRD_WDT_INT_CLEAR_BIT, wdt->base + SPRD_WDT_INT_CLR); in sprd_wdt_isr()
87 sprd_wdt_lock(wdt->base); in sprd_wdt_isr()
88 watchdog_notify_pretimeout(&wdt->wdd); in sprd_wdt_isr()
92 static u32 sprd_wdt_get_cnt_value(struct sprd_wdt *wdt) in sprd_wdt_get_cnt_value() argument
96 val = readl_relaxed(wdt->base + SPRD_WDT_CNT_HIGH) << in sprd_wdt_get_cnt_value()
98 val |= readl_relaxed(wdt->base + SPRD_WDT_CNT_LOW) & in sprd_wdt_get_cnt_value()
104 static int sprd_wdt_load_value(struct sprd_wdt *wdt, u32 timeout, in sprd_wdt_load_value() argument
116 val = readl_relaxed(wdt->base + SPRD_WDT_INT_RAW); in sprd_wdt_load_value()
[all …]
Ds3c2410_wdt.c164 { .compatible = "samsung,s3c2410-wdt",
166 { .compatible = "samsung,s3c6410-wdt",
168 { .compatible = "samsung,exynos5250-wdt",
170 { .compatible = "samsung,exynos5420-wdt",
172 { .compatible = "samsung,exynos7-wdt",
181 .name = "s3c2410-wdt",
203 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask) in s3c2410wdt_mask_and_disable_reset() argument
206 u32 mask_val = 1 << wdt->drv_data->mask_bit; in s3c2410wdt_mask_and_disable_reset()
210 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG)) in s3c2410wdt_mask_and_disable_reset()
216 ret = regmap_update_bits(wdt->pmureg, in s3c2410wdt_mask_and_disable_reset()
[all …]
Dsp805_wdt.c2 * drivers/char/watchdog/sp805-wdt.c
36 #define MODULE_NAME "sp805-wdt"
57 * struct sp805_wdt: sp805 wdt device structure
60 * @base: base address of wdt
61 * @clk: clock structure of wdt
62 * @adev: amba device structure of wdt
63 * @status: current status of wdt
81 /* returns true if wdt is running; otherwise returns false */
84 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd); in wdt_is_running() local
85 u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL); in wdt_is_running()
[all …]
Dmei_wdt.c161 * @wdt: mei watchdog device
166 static int mei_wdt_ping(struct mei_wdt *wdt) in mei_wdt_ping() argument
177 req.timeout = wdt->timeout; in mei_wdt_ping()
179 ret = mei_cldev_send(wdt->cldev, (u8 *)&req, req_len); in mei_wdt_ping()
189 * @wdt: mei watchdog device
194 static int mei_wdt_stop(struct mei_wdt *wdt) in mei_wdt_stop() argument
206 ret = mei_cldev_send(wdt->cldev, (u8 *)&req, req_len); in mei_wdt_stop()
222 struct mei_wdt *wdt = watchdog_get_drvdata(wdd); in mei_wdt_ops_start() local
224 wdt->state = MEI_WDT_START; in mei_wdt_ops_start()
225 wdd->timeout = wdt->timeout; in mei_wdt_ops_start()
[all …]
Dmlx_wdt.c57 static void mlxreg_wdt_check_card_reset(struct mlxreg_wdt *wdt) in mlxreg_wdt_check_card_reset() argument
63 if (wdt->reset_idx == -EINVAL) in mlxreg_wdt_check_card_reset()
66 if (!(wdt->wdd.info->options & WDIOF_CARDRESET)) in mlxreg_wdt_check_card_reset()
69 reg_data = &wdt->pdata->data[wdt->reset_idx]; in mlxreg_wdt_check_card_reset()
70 rc = regmap_read(wdt->regmap, reg_data->reg, &regval); in mlxreg_wdt_check_card_reset()
73 wdt->wdd.bootstatus = WDIOF_CARDRESET; in mlxreg_wdt_check_card_reset()
74 dev_info(wdt->wdd.parent, in mlxreg_wdt_check_card_reset()
82 struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd); in mlxreg_wdt_start() local
83 struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx]; in mlxreg_wdt_start()
85 return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask, in mlxreg_wdt_start()
[all …]
Dat91sam9_wdt.c40 #define wdt_read(wdt, field) \ argument
41 readl_relaxed((wdt)->base + (field))
43 writel_relaxed((val), (wdt)->base + (field))
88 unsigned long heartbeat; /* WDT heartbeat in jiffies */
98 struct at91wdt *wdt = (struct at91wdt *)dev_id; in wdt_interrupt() local
100 if (wdt_read(wdt, AT91_WDT_SR)) { in wdt_interrupt()
101 pr_crit("at91sam9 WDT software reset\n"); in wdt_interrupt()
112 static inline void at91_wdt_reset(struct at91wdt *wdt) in at91_wdt_reset() argument
114 wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); in at91_wdt_reset()
122 struct at91wdt *wdt = from_timer(wdt, t, timer); in at91_ping() local
[all …]
Dbcm7038_wdt.c39 struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); in bcm7038_wdt_set_timeout_reg() local
42 timeout = wdt->rate * wdog->timeout; in bcm7038_wdt_set_timeout_reg()
44 writel(timeout, wdt->base + WDT_TIMEOUT_REG); in bcm7038_wdt_set_timeout_reg()
49 struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); in bcm7038_wdt_ping() local
51 writel(WDT_START_1, wdt->base + WDT_CMD_REG); in bcm7038_wdt_ping()
52 writel(WDT_START_2, wdt->base + WDT_CMD_REG); in bcm7038_wdt_ping()
67 struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); in bcm7038_wdt_stop() local
69 writel(WDT_STOP_1, wdt->base + WDT_CMD_REG); in bcm7038_wdt_stop()
70 writel(WDT_STOP_2, wdt->base + WDT_CMD_REG); in bcm7038_wdt_stop()
88 struct bcm7038_watchdog *wdt = watchdog_get_drvdata(wdog); in bcm7038_wdt_get_timeleft() local
[all …]
Dpm8916_wdt.c41 struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev); in pm8916_wdt_start() local
43 return regmap_update_bits(wdt->regmap, in pm8916_wdt_start()
44 wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2, in pm8916_wdt_start()
50 struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev); in pm8916_wdt_stop() local
52 return regmap_update_bits(wdt->regmap, in pm8916_wdt_stop()
53 wdt->baseaddr + PON_PMIC_WD_RESET_S2_CTL2, in pm8916_wdt_stop()
59 struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev); in pm8916_wdt_ping() local
61 return regmap_update_bits(wdt->regmap, in pm8916_wdt_ping()
62 wdt->baseaddr + PON_PMIC_WD_RESET_PET, in pm8916_wdt_ping()
68 struct pm8916_wdt *wdt = watchdog_get_drvdata(wdev); in pm8916_wdt_configure_timers() local
[all …]
Dda9062_wdt.c38 static unsigned int da9062_wdt_read_timeout(struct da9062_watchdog *wdt) in da9062_wdt_read_timeout() argument
42 regmap_read(wdt->hw->regmap, DA9062AA_CONTROL_D, &val); in da9062_wdt_read_timeout()
59 static int da9062_reset_watchdog_timer(struct da9062_watchdog *wdt) in da9062_reset_watchdog_timer() argument
61 return regmap_update_bits(wdt->hw->regmap, DA9062AA_CONTROL_F, in da9062_reset_watchdog_timer()
66 static int da9062_wdt_update_timeout_register(struct da9062_watchdog *wdt, in da9062_wdt_update_timeout_register() argument
69 struct da9062 *chip = wdt->hw; in da9062_wdt_update_timeout_register()
86 struct da9062_watchdog *wdt = watchdog_get_drvdata(wdd); in da9062_wdt_start() local
90 selector = da9062_wdt_timeout_to_sel(wdt->wdtdev.timeout); in da9062_wdt_start()
91 ret = da9062_wdt_update_timeout_register(wdt, selector); in da9062_wdt_start()
93 dev_err(wdt->hw->dev, "Watchdog failed to start (err = %d)\n", in da9062_wdt_start()
[all …]
Dzx2967_wdt.c54 static inline u32 zx2967_wdt_readl(struct zx2967_wdt *wdt, u16 reg) in zx2967_wdt_readl() argument
56 return readl_relaxed(wdt->reg_base + reg); in zx2967_wdt_readl()
59 static inline void zx2967_wdt_writel(struct zx2967_wdt *wdt, u16 reg, u32 val) in zx2967_wdt_writel() argument
61 writel_relaxed(val | ZX2967_WDT_WRITEKEY, wdt->reg_base + reg); in zx2967_wdt_writel()
64 static void zx2967_wdt_refresh(struct zx2967_wdt *wdt) in zx2967_wdt_refresh() argument
68 val = zx2967_wdt_readl(wdt, ZX2967_WDT_REFRESH_REG); in zx2967_wdt_refresh()
76 zx2967_wdt_writel(wdt, ZX2967_WDT_REFRESH_REG, in zx2967_wdt_refresh()
83 struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd); in zx2967_wdt_set_timeout() local
91 zx2967_wdt_writel(wdt, ZX2967_WDT_CFG_REG, in zx2967_wdt_set_timeout()
93 zx2967_wdt_writel(wdt, ZX2967_WDT_LOAD_REG, in zx2967_wdt_set_timeout()
[all …]
Dbcm47xx_wdt.c50 struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); in bcm47xx_wdt_hard_keepalive() local
52 wdt->timer_set_ms(wdt, wdd->timeout * 1000); in bcm47xx_wdt_hard_keepalive()
64 struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); in bcm47xx_wdt_hard_stop() local
66 wdt->timer_set(wdt, 0); in bcm47xx_wdt_hard_stop()
74 struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); in bcm47xx_wdt_hard_set_timeout() local
75 u32 max_timer = wdt->max_timer_ms; in bcm47xx_wdt_hard_set_timeout()
90 struct bcm47xx_wdt *wdt = bcm47xx_wdt_get(wdd); in bcm47xx_wdt_restart() local
92 wdt->timer_set(wdt, 1); in bcm47xx_wdt_restart()
108 struct bcm47xx_wdt *wdt = from_timer(wdt, t, soft_timer); in bcm47xx_wdt_soft_timer_tick() local
109 u32 next_tick = min(wdt->wdd.timeout * 1000, wdt->max_timer_ms); in bcm47xx_wdt_soft_timer_tick()
[all …]
Dqcom-wdt.c54 static void __iomem *wdt_addr(struct qcom_wdt *wdt, enum wdt_reg reg) in wdt_addr() argument
56 return wdt->base + wdt->layout[reg]; in wdt_addr()
76 struct qcom_wdt *wdt = to_qcom_wdt(wdd); in qcom_wdt_start() local
79 writel(0, wdt_addr(wdt, WDT_EN)); in qcom_wdt_start()
80 writel(1, wdt_addr(wdt, WDT_RST)); in qcom_wdt_start()
81 writel(bark * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME)); in qcom_wdt_start()
82 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME)); in qcom_wdt_start()
83 writel(QCOM_WDT_ENABLE, wdt_addr(wdt, WDT_EN)); in qcom_wdt_start()
89 struct qcom_wdt *wdt = to_qcom_wdt(wdd); in qcom_wdt_stop() local
91 writel(0, wdt_addr(wdt, WDT_EN)); in qcom_wdt_stop()
[all …]
Dpic32-wdt.c45 static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt *wdt) in pic32_wdt_is_win_enabled() argument
47 return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN); in pic32_wdt_is_win_enabled()
50 static inline u32 pic32_wdt_get_post_scaler(struct pic32_wdt *wdt) in pic32_wdt_get_post_scaler() argument
52 u32 v = readl(wdt->regs + WDTCON_REG); in pic32_wdt_get_post_scaler()
57 static inline u32 pic32_wdt_get_clk_id(struct pic32_wdt *wdt) in pic32_wdt_get_clk_id() argument
59 u32 v = readl(wdt->regs + WDTCON_REG); in pic32_wdt_get_clk_id()
64 static int pic32_wdt_bootstatus(struct pic32_wdt *wdt) in pic32_wdt_bootstatus() argument
66 u32 v = readl(wdt->rst_base); in pic32_wdt_bootstatus()
68 writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base)); in pic32_wdt_bootstatus()
73 static u32 pic32_wdt_get_timeout_secs(struct pic32_wdt *wdt, struct device *dev) in pic32_wdt_get_timeout_secs() argument
[all …]
Dmax63xx_wdt.c56 void (*ping)(struct max63xx_wdt *wdt);
57 void (*set)(struct max63xx_wdt *wdt, u8 set);
122 struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd); in max63xx_wdt_ping() local
124 wdt->ping(wdt); in max63xx_wdt_ping()
130 struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd); in max63xx_wdt_start() local
132 wdt->set(wdt, wdt->timeout->wdset); in max63xx_wdt_start()
135 if (wdt->timeout->tdelay == 0) in max63xx_wdt_start()
136 wdt->ping(wdt); in max63xx_wdt_start()
142 struct max63xx_wdt *wdt = watchdog_get_drvdata(wdd); in max63xx_wdt_stop() local
144 wdt->set(wdt, MAX6369_WDSET_DISABLED); in max63xx_wdt_stop()
[all …]
Dbcm_kona_wdt.c58 static int secure_register_read(struct bcm_kona_wdt *wdt, uint32_t offset) in secure_register_read() argument
71 val = readl_relaxed(wdt->base + offset); in secure_register_read()
77 if (count > wdt->busy_count) in secure_register_read()
78 wdt->busy_count = count; in secure_register_read()
97 struct bcm_kona_wdt *wdt = s->private; in bcm_kona_show() local
99 if (!wdt) { in bcm_kona_show()
104 spin_lock_irqsave(&wdt->lock, flags); in bcm_kona_show()
105 ctl_val = secure_register_read(wdt, SECWDOG_CTRL_REG); in bcm_kona_show()
106 cur_val = secure_register_read(wdt, SECWDOG_COUNT_REG); in bcm_kona_show()
107 spin_unlock_irqrestore(&wdt->lock, flags); in bcm_kona_show()
[all …]
Daspeed_wdt.c35 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
36 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
37 { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
104 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count) in aspeed_wdt_enable() argument
106 wdt->ctrl |= WDT_CTRL_ENABLE; in aspeed_wdt_enable()
108 writel(0, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
109 writel(count, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_enable()
110 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_enable()
111 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
116 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd); in aspeed_wdt_start() local
[all …]
Dni903x_wdt.c56 static void ni903x_start(struct ni903x_wdt *wdt) in ni903x_start() argument
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
67 struct ni903x_wdt *wdt = watchdog_get_drvdata(wdd); in ni903x_wdd_set_timeout() local
70 outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2); in ni903x_wdd_set_timeout()
71 outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1); in ni903x_wdd_set_timeout()
72 outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0); in ni903x_wdd_set_timeout()
81 struct ni903x_wdt *wdt = watchdog_get_drvdata(wdd); in ni903x_wdd_get_timeleft() local
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
[all …]
Ddigicolor_wdt.c34 static void dc_wdt_set(struct dc_wdt *wdt, u32 ticks) in dc_wdt_set() argument
38 spin_lock_irqsave(&wdt->lock, flags); in dc_wdt_set()
40 writel_relaxed(0, wdt->base + TIMER_A_CONTROL); in dc_wdt_set()
41 writel_relaxed(ticks, wdt->base + TIMER_A_COUNT); in dc_wdt_set()
43 wdt->base + TIMER_A_CONTROL); in dc_wdt_set()
45 spin_unlock_irqrestore(&wdt->lock, flags); in dc_wdt_set()
51 struct dc_wdt *wdt = watchdog_get_drvdata(wdog); in dc_wdt_restart() local
53 dc_wdt_set(wdt, 1); in dc_wdt_restart()
62 struct dc_wdt *wdt = watchdog_get_drvdata(wdog); in dc_wdt_start() local
64 dc_wdt_set(wdt, wdog->timeout * clk_get_rate(wdt->clk)); in dc_wdt_start()
[all …]
Dcadence_wdt.c3 * Cadence WDT driver - Used by Xilinx Zynq
85 static inline void cdns_wdt_writereg(struct cdns_wdt *wdt, u32 offset, u32 val) in cdns_wdt_writereg() argument
87 writel_relaxed(val, wdt->regs + offset); in cdns_wdt_writereg()
92 /* Register Offsets for the WDT */
102 #define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
126 struct cdns_wdt *wdt = watchdog_get_drvdata(wdd); in cdns_wdt_stop() local
128 spin_lock(&wdt->io_lock); in cdns_wdt_stop()
129 cdns_wdt_writereg(wdt, CDNS_WDT_ZMR_OFFSET, in cdns_wdt_stop()
131 spin_unlock(&wdt->io_lock); in cdns_wdt_stop()
147 struct cdns_wdt *wdt = watchdog_get_drvdata(wdd); in cdns_wdt_reload() local
[all …]
Dtwl4030_wdt.c29 static int twl4030_wdt_start(struct watchdog_device *wdt) in twl4030_wdt_start() argument
31 return twl4030_wdt_write(wdt->timeout + 1); in twl4030_wdt_start()
34 static int twl4030_wdt_stop(struct watchdog_device *wdt) in twl4030_wdt_stop() argument
39 static int twl4030_wdt_set_timeout(struct watchdog_device *wdt, in twl4030_wdt_set_timeout() argument
42 wdt->timeout = timeout; in twl4030_wdt_set_timeout()
61 struct watchdog_device *wdt; in twl4030_wdt_probe() local
63 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL); in twl4030_wdt_probe()
64 if (!wdt) in twl4030_wdt_probe()
67 wdt->info = &twl4030_wdt_info; in twl4030_wdt_probe()
68 wdt->ops = &twl4030_wdt_ops; in twl4030_wdt_probe()
[all …]
Drn5t618_wdt.c14 #define DRIVER_NAME "rn5t618-wdt"
50 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_set_timeout() local
61 ret = regmap_update_bits(wdt->rn5t618->regmap, RN5T618_WATCHDOG, in rn5t618_wdt_set_timeout()
72 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_start() local
80 ret = regmap_update_bits(wdt->rn5t618->regmap, RN5T618_REPCNT, in rn5t618_wdt_start()
87 ret = regmap_update_bits(wdt->rn5t618->regmap, RN5T618_WATCHDOG, in rn5t618_wdt_start()
94 return regmap_update_bits(wdt->rn5t618->regmap, RN5T618_PWRIREN, in rn5t618_wdt_start()
101 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_stop() local
103 return regmap_update_bits(wdt->rn5t618->regmap, RN5T618_WATCHDOG, in rn5t618_wdt_stop()
109 struct rn5t618_wdt *wdt = watchdog_get_drvdata(wdt_dev); in rn5t618_wdt_ping() local
[all …]
Dnic7018_wdt.c89 struct nic7018_wdt *wdt = watchdog_get_drvdata(wdd); in nic7018_set_timeout() local
96 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
99 wdt->period = config->period; in nic7018_set_timeout()
106 struct nic7018_wdt *wdt = watchdog_get_drvdata(wdd); in nic7018_start() local
111 control = inb(wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
112 outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
114 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
116 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
117 outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL); in nic7018_start()
124 struct nic7018_wdt *wdt = watchdog_get_drvdata(wdd); in nic7018_stop() local
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Drenesas,wdt.yaml4 $id: http://devicetree.org/schemas/watchdog/renesas,wdt.yaml#
7 title: Renesas Watchdog Timer (WDT) Controller
21 - renesas,r7s72100-wdt # RZ/A1
22 - renesas,r7s9210-wdt # RZ/A2
23 - const: renesas,rza-wdt # RZ/A
27 - renesas,r8a7742-wdt # RZ/G1H
28 - renesas,r8a7743-wdt # RZ/G1M
29 - renesas,r8a7744-wdt # RZ/G1N
30 - renesas,r8a7745-wdt # RZ/G1E
31 - renesas,r8a77470-wdt # RZ/G1C
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Dmtk-wdt.txt6 "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
7 "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712
8 "mediatek,mt6589-wdt": for MT6589
9 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
10 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
11 "mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
12 "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
13 "mediatek,mt8183-wdt", "mediatek,mt6589-wdt": for MT8183
14 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
25 compatible = "mediatek,mt8183-wdt",
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