| /kernel/linux/linux-5.10/sound/soc/intel/skylake/ |
| D | skl-sst-dsp.c | 31 * successful first boot. Hence core 0 will be running and other cores
39 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; in skl_dsp_init_core_state()
40 skl->cores.usage_count[SKL_DSP_CORE0_ID] = 1; in skl_dsp_init_core_state()
42 for (i = SKL_DSP_CORE0_ID + 1; i < skl->cores.count; i++) { in skl_dsp_init_core_state()
43 skl->cores.state[i] = SKL_DSP_RESET; in skl_dsp_init_core_state()
44 skl->cores.usage_count[i] = 0; in skl_dsp_init_core_state()
48 /* Get the mask for all enabled cores */
55 core_mask = SKL_DSP_CORES_MASK(skl->cores.count); in skl_dsp_get_enabled_cores()
59 /* Cores having CPA bit set */ in skl_dsp_get_enabled_cores()
63 /* And cores having CRST bit cleared */ in skl_dsp_get_enabled_cores()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/ |
| D | lockup-watchdogs.rst | 67 By default, the watchdog runs on all online cores. However, on a
69 on the housekeeping cores, not the cores specified in the "nohz_full"
71 the "nohz_full" cores, we would have to run timer ticks to activate
73 from protecting the user code on those cores from the kernel.
74 Of course, disabling it by default on the nohz_full cores means that
75 when those cores do enter the kernel, by default we will not be
77 to continue to run on the housekeeping (non-tickless) cores means
78 that we will continue to detect lockups properly on those cores.
80 In either case, the set of cores excluded from running the watchdog
82 nohz_full cores, this may be useful for debugging a case where the
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/include/asm/octeon/ |
| D | cvmx-coremask.h | 11 * Module to support operations on bitmap of cores. Coremask can be used to
12 * select a specific core, a group of cores, or all available cores, for
22 * Node 0: Cores 0 - 47
23 * Node 1: Cores 128 - 175
24 * Node 2: Cores 256 - 303
25 * Node 3: Cores 384 - 431
|
| /kernel/linux/linux-5.10/drivers/remoteproc/ |
| D | ti_k3_r5_remoteproc.c | 74 * @cores: list of R5 cores within the cluster
79 struct list_head cores; member
254 /* assert local reset on all applicable cores */ in k3_r5_lockstep_reset()
255 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
265 /* disable PSC modules on all applicable cores */ in k3_r5_lockstep_reset()
266 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
279 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
284 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem); in k3_r5_lockstep_reset()
286 list_for_each_entry_from_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
299 /* enable PSC modules on all applicable cores */ in k3_r5_lockstep_release()
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | cache.json | 535 …clusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket…
546 …clusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket…
748 …efetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M…
760 …t needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
772 … & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean respo…
796 …emand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S …
808 …efetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M…
820 …t needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
832 … & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean respo…
856 …"Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S …
[all …]
|
| D | uncore.json | 199 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
200 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
211 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
212 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
271 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
272 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
283 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
284 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
|
| /kernel/linux/linux-5.10/drivers/crypto/cavium/cpt/ |
| D | cptpf_main.c | 25 * Disable cores specified by coremask
38 /* Disengage the cores from groups */ in cpt_disable_cores()
45 dev_err(dev, "Cores still busy %llx", coremask); in cpt_disable_cores()
54 /* Disable the cores */ in cpt_disable_cores()
62 * Enable cores specified by coremask
139 /* Assumes 0-9 are SE cores for UCODE_BASE registers and in cpt_load_microcode()
173 dev_err(dev, "Requested for more cores than available AE cores\n"); in do_cpt_init()
184 /* Convert requested cores to mask */ in do_cpt_init()
199 /* Enable AE cores for the group mask */ in do_cpt_init()
203 dev_err(dev, "Requested for more cores than available SE cores\n"); in do_cpt_init()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
|
| /kernel/linux/linux-5.10/drivers/phy/broadcom/ |
| D | phy-bcm-sr-pcie.c | 85 /* PIPEMUX = 3, RC 2x8, cores 0, 7 */
87 /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
89 /* PIPEMUX = 5, RC 8x2, all 8 cores */
91 /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
93 /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
95 /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
97 /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
99 /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
101 /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
103 /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | snps,arc-timer.txt | 4 - Two idential copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | uncore-power.json | 10 …cy event that tracks the number of cores that are in C0. It can be used by itself to get the aver…
21 …cy event that tracks the number of cores that are in C3. It can be used by itself to get the aver…
32 …cy event that tracks the number of cores that are in C6. It can be used by itself to get the aver…
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | uncore-power.json | 10 …cy event that tracks the number of cores that are in C0. It can be used by itself to get the aver…
21 …cy event that tracks the number of cores that are in C3. It can be used by itself to get the aver…
32 …cy event that tracks the number of cores that are in C6. It can be used by itself to get the aver…
|
| D | cache.json | 841 …"BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in…
846 …ption": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S …
854 …ounts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M…
859 …ounts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M…
867 …nts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S …
872 …nts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S …
880 …mand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M…
885 …mand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M…
893 …n": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
898 …n": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | uncore-power.json | 10 …cy event that tracks the number of cores that are in C0. It can be used by itself to get the aver…
21 …cy event that tracks the number of cores that are in C3. It can be used by itself to get the aver…
32 …cy event that tracks the number of cores that are in C6. It can be used by itself to get the aver…
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
77 cores in a test chip on the core tile. See ARM DDI 0498D.
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
85 cores in a big.LITTLE configuration. It also features the MALI T624
|
| /kernel/linux/linux-5.10/drivers/bcma/ |
| D | main.c | 91 list_for_each_entry(core, &bus->cores, list) { in bcma_find_core_unit()
271 INIT_LIST_HEAD(&bus->cores); in bcma_init_bus()
295 list_for_each_entry(core, &bus->cores, list) { in bcma_register_devices()
296 /* We support that cores ourself */ in bcma_register_devices()
309 /* Early cores were already registered */ in bcma_register_devices()
363 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
372 /* Now noone uses internally-handled cores, we can free them */ in bcma_unregister_cores()
373 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
384 /* Scan for devices (cores) */ in bcma_bus_register()
408 /* Cores providing flash access go before SPROM init */ in bcma_bus_register()
[all …]
|
| /kernel/linux/linux-5.10/tools/power/cpupower/man/ |
| D | cpupower-set.1 | 13 Some options are platform wide, some affect single cores. By default values
14 are applied on all cores. How to modify single core configurations is
16 option affects the whole system or can be applied to individual cores is
48 This option can be applied to individual cores only via the \-\-cpu option,
|
| D | cpupower-info.1 | 12 Some options are platform wide, some affect single cores. By default values
14 settings of all cores, see cpupower(1) how to choose specific cores.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
|
| /kernel/linux/linux-5.10/arch/csky/include/asm/ |
| D | barrier.h | 15 * sync.s: inherit from sync, but also shareable to other cores
21 * and shareable to other cores
24 * and shareable to other cores
27 * and shareable to other cores
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca15-tc1.dts | 199 volt-cores {
203 regulator-name = "Cores";
207 label = "Cores";
210 amp-cores {
211 /* Total current for the two cores */
214 label = "Cores";
224 power-cores {
228 label = "Cores";
235 label = "Cores";
|
| /kernel/linux/linux-5.10/tools/power/cpupower/lib/ |
| D | cpupower.h | 6 /* Amount of CPU cores, packages and threads per core in the system */
7 unsigned int cores; member
11 /* Array gets mallocated with cores entries, holding per core info */
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv50/ |
| D | core.c | 44 } cores[] = { in nv50_core_new() local
64 cid = nvif_mclass(&disp->disp->object, cores); in nv50_core_new()
70 return cores[cid].new(drm, cores[cid].oclass, pcore); in nv50_core_new()
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswell/ |
| D | cache.json | 817 …"PublicDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M s…
825 …"BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M st…
830 …"PublicDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and th…
838 …"BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the…
843 … all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
851 … all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S …
856 … demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M…
864 … demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M…
869 …Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S …
877 …Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/ |
| D | uncore.json | 199 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
200 …ntroller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic…
211 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
212 …: "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic…
271 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
272 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
283 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
284 …ontroller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphic…
|