| /kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.c | 10 #define DSS_SUBSYS_NAME "DISPC"
37 #include "dispc.h"
41 /* DISPC */
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
57 /* DISPC has feature id */
100 int (*calc_scaling)(struct dispc_device *dispc,
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| D | omapdss.h | 404 /* DISPC channel for this output */
523 /* dispc ops */
526 u32 (*read_irqstatus)(struct dispc_device *dispc);
527 void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);
528 void (*write_irqenable)(struct dispc_device *dispc, u32 mask);
530 int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,
532 void (*free_irq)(struct dispc_device *dispc, void *dev_id);
534 int (*runtime_get)(struct dispc_device *dispc);
535 void (*runtime_put)(struct dispc_device *dispc);
537 int (*get_num_ovls)(struct dispc_device *dispc);
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| D | dss.h | 259 struct dispc_device *dispc; member
390 /* DISPC */
391 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
393 int dispc_runtime_get(struct dispc_device *dispc);
394 void dispc_runtime_put(struct dispc_device *dispc);
396 void dispc_enable_sidle(struct dispc_device *dispc);
397 void dispc_disable_sidle(struct dispc_device *dispc);
399 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
400 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
401 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
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| D | Kconfig | 34 dispc, dsi, hdmi and rfbi.
44 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
113 With this you can make sure that DISPC FCK is at least
118 DISPC FCK. However, the FCK will at minimum be
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| D | sdi.c | 68 return dispc_div_calc(ctx->sdi->dss->dispc, fck, in dpi_calc_dss_cb()
209 r = dispc_runtime_get(sdi->dss->dispc); in sdi_bridge_enable()
227 * normally write them to DISPC registers when enabling the output. in sdi_bridge_enable()
232 * It seems just writing to the DISPC register is enough, and we don't in sdi_bridge_enable()
236 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel, in sdi_bridge_enable()
256 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_enable()
269 dispc_runtime_put(sdi->dss->dispc); in sdi_bridge_disable()
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| D | dpi.c | 99 * would also be used for DISPC fclk. Meaning, when the DPI output is in dpi_get_clk_src()
100 * disabled, DISPC clock will be disabled, and TV out will stop. in dpi_get_clk_src()
178 static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc, in dpi_calc_hsdiv_cb() argument
184 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; in dpi_calc_hsdiv_cb()
186 return dispc_div_calc(ctx->dpi->dss->dispc, dispc, in dpi_calc_hsdiv_cb()
214 return dispc_div_calc(ctx->dpi->dss->dispc, fck, in dpi_calc_dss_cb()
494 r = dispc_runtime_get(dpi->dss->dispc); in dpi_bridge_enable()
528 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_enable()
546 dispc_runtime_put(dpi->dss->dispc); in dpi_bridge_disable()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/tidss/ |
| D | tidss_dispc.c | 310 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val) in dispc_write() argument
312 iowrite32(val, dispc->base_common + reg); in dispc_write()
315 static u32 dispc_read(struct dispc_device *dispc, u16 reg) in dispc_read() argument
317 return ioread32(dispc->base_common + reg); in dispc_read()
321 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val) in dispc_vid_write() argument
323 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
328 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg) in dispc_vid_read() argument
330 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
335 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport, in dispc_ovr_write() argument
338 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
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| D | tidss_dispc.h | 92 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
93 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
95 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
97 void dispc_ovr_enable_layer(struct dispc_device *dispc,
100 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
102 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
104 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
105 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
106 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
107 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
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| D | tidss_crtc.c | 40 busy = dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_finish_page_flip()
92 struct dispc_device *dispc = tidss->dispc; in tidss_crtc_atomic_check() local
105 ok = dispc_vp_mode_valid(dispc, hw_videoport, mode); in tidss_crtc_atomic_check()
112 return dispc_vp_bus_check(dispc, hw_videoport, state); in tidss_crtc_atomic_check()
153 dispc_ovr_set_plane(tidss->dispc, tplane->hw_plane_id, in tidss_crtc_position_planes()
158 dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, in tidss_crtc_position_planes()
188 if (WARN_ON(dispc_vp_go_busy(tidss->dispc, tcrtc->hw_videoport))) in tidss_crtc_atomic_flush()
196 dispc_vp_setup(tidss->dispc, tcrtc->hw_videoport, crtc->state, false); in tidss_crtc_atomic_flush()
204 dispc_vp_go(tidss->dispc, tcrtc->hw_videoport); in tidss_crtc_atomic_flush()
228 r = dispc_vp_set_clk_rate(tidss->dispc, tcrtc->hw_videoport, in tidss_crtc_atomic_enable()
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| D | tidss_irq.c | 15 /* call with wait_lock and dispc runtime held */
20 dispc_set_irqenable(tidss->dispc, tidss->irq_mask); in tidss_irq_update()
63 irqstatus = dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_handler()
104 dispc_set_irqenable(tidss->dispc, 0); in tidss_irq_preinstall()
105 dispc_read_and_clear_irqstatus(tidss->dispc); in tidss_irq_preinstall()
144 dispc_set_irqenable(tidss->dispc, 0); in tidss_irq_uninstall()
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| D | tidss_drv.c | 57 return dispc_runtime_suspend(tidss->dispc); in tidss_pm_runtime_suspend()
67 r = dispc_runtime_resume(tidss->dispc); in tidss_pm_runtime_resume()
152 dev_err(dev, "failed to initialize dispc: %d\n", ret); in tidss_probe()
160 dispc_runtime_resume(tidss->dispc); in tidss_probe()
203 dispc_runtime_suspend(tidss->dispc); in tidss_probe()
226 dispc_runtime_suspend(tidss->dispc); in tidss_remove()
230 /* devm allocated dispc goes away with the dev so mark it NULL */ in tidss_remove()
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| D | tidss_plane.c | 93 ret = dispc_plane_check(tidss->dispc, hw_plane, state, hw_videoport); in tidss_plane_atomic_check()
113 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_update()
119 ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, in tidss_plane_atomic_update()
125 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_update()
129 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true); in tidss_plane_atomic_update()
141 dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); in tidss_plane_atomic_disable()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/omapdrm/ |
| D | omap_irq.c | 18 /* call with wait_lock and dispc runtime held */
32 priv->dispc_ops->write_irqenable(priv->dispc, irqmask); in omap_irq_update()
86 priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, channel); in omap_irq_enable_framedone()
124 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, in omap_irq_enable_vblank()
151 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, in omap_irq_disable_vblank()
216 irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc); in omap_irq_handler()
217 priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus); in omap_irq_handler()
218 priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */ in omap_irq_handler()
226 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) { in omap_irq_handler()
231 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel)) in omap_irq_handler()
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| D | omap_crtc.c | 106 priv->dispc_ops->mgr_enable(priv->dispc, channel, true); in omap_crtc_dss_start_update()
131 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
144 framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc, in omap_crtc_set_enabled()
146 vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel); in omap_crtc_set_enabled()
153 * FRAMEDONE to know that DISPC has finished with the output. in omap_crtc_set_enabled()
166 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable); in omap_crtc_set_enabled()
189 priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel, in omap_crtc_dss_enable()
224 priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel, in omap_crtc_dss_set_lcd_config()
300 * If the dispc is busy we're racing the flush operation. Try again on in omap_crtc_vblank_irq()
303 if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) { in omap_crtc_vblank_irq()
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| D | omap_plane.c | 73 ret = priv->dispc_ops->ovl_setup(priv->dispc, omap_plane->id, &info, in omap_plane_atomic_update()
79 priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false); in omap_plane_atomic_update()
83 priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, true); in omap_plane_atomic_update()
96 priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false); in omap_plane_atomic_disable()
255 unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); in omap_plane_init()
274 formats = priv->dispc_ops->ovl_get_color_modes(priv->dispc, id); in omap_plane_init()
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| D | omap_drv.c | 72 priv->dispc_ops->runtime_get(priv->dispc); in omap_atomic_commit_tail()
78 /* With the current dss dispc implementation we have to enable in omap_atomic_commit_tail()
79 * the new modeset before we can commit planes. The dispc ovl in omap_atomic_commit_tail()
86 * interrupt. The dispc implementation should be fixed so that in omap_atomic_commit_tail()
116 priv->dispc_ops->runtime_put(priv->dispc); in omap_atomic_commit_tail()
195 unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc); in omap_modeset_init_properties()
231 int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc); in omap_modeset_init()
232 int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc); in omap_modeset_init()
316 * Populate the pipeline lookup table by DISPC channel. Only one display in omap_modeset_init()
595 priv->dispc = dispc_get_dispc(priv->dss); in omapdrm_init()
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| /kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.c | 3 * linux/drivers/video/omap2/dss/dispc.c
12 #define DSS_SUBSYS_NAME "DISPC"
37 #include "dispc.h"
39 /* DISPC */
84 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
127 } dispc; variable
253 __raw_writel(val, dispc.base + idx); in dispc_write_reg()
258 return __raw_readl(dispc.base + idx); in dispc_read_reg()
274 spin_lock_irqsave(&dispc.control_lock, flags); in mgr_fld_write()
279 spin_unlock_irqrestore(&dispc.control_lock, flags); in mgr_fld_write()
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| D | Kconfig | 24 dispc, dsi, hdmi and rfbi.
33 <debugfs>/omapdss/dispc_irq for DISPC interrupts, and
91 With this you can make sure that DISPC FCK is at least
96 DISPC FCK. However, the FCK will at minimum be
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| D | Makefile | 5 omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
9 dispc-compat.o display-sysfs.o
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ti/ |
| D | ti,dra7-dss.txt | 29 - DISPC
39 DISPC
43 - compatible: "ti,dra7-dispc"
46 - interrupts: the DISPC interrupt
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap5-dss.txt | 18 - DISPC
28 DISPC
32 - compatible: "ti,omap5-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap2-dss.txt | 22 DISPC
26 - compatible: "ti,omap2-dispc"
29 - interrupts: the DISPC interrupt
32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap4-dss.txt | 18 - DISPC
28 DISPC
32 - compatible: "ti,omap4-dispc"
35 - interrupts: the DISPC interrupt
40 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap3-dss.txt | 29 DISPC
33 - compatible: "ti,omap3-dispc"
36 - interrupts: the DISPC interrupt
41 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap-dss.txt | 11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
18 DISPC is the display controller, which reads pixels from the memory and outputs
59 dispc@58001000 {
60 compatible = "ti,omap4-dispc";
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