| /kernel/linux/linux-5.10/drivers/clk/mmp/ |
| D | clk-frac.c | 38 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_round_rate()
57 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_recalc_rate() local
64 num = (val >> masks->num_shift) & masks->num_mask; in clk_factor_recalc_rate()
67 den = (val >> masks->den_shift) & masks->den_mask; in clk_factor_recalc_rate()
74 do_div(rate, num * factor->masks->factor); in clk_factor_recalc_rate()
84 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_set_rate() local
93 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_set_rate()
106 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_set_rate()
107 val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; in clk_factor_set_rate()
109 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_set_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/spear/ |
| D | clk-aux-synth.c | 80 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; in clk_aux_recalc_rate()
81 if (eqn == aux->masks->eq1_mask) in clk_aux_recalc_rate()
85 num = (val >> aux->masks->xscale_sel_shift) & in clk_aux_recalc_rate()
86 aux->masks->xscale_sel_mask; in clk_aux_recalc_rate()
89 den *= (val >> aux->masks->yscale_sel_shift) & in clk_aux_recalc_rate()
90 aux->masks->yscale_sel_mask; in clk_aux_recalc_rate()
114 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); in clk_aux_set_rate()
115 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << in clk_aux_set_rate()
116 aux->masks->eq_sel_shift; in clk_aux_set_rate()
117 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); in clk_aux_set_rate()
[all …]
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| /kernel/linux/linux-5.10/sound/soc/codecs/ |
| D | tscs42xx.h | 124 /* Field Masks */
132 /* Register Masks */
147 /* Field Masks */
155 /* Register Masks */
170 /* Field Masks */
178 /* Register Masks */
195 /* Field Masks */
203 /* Register Masks */
220 /* Field Masks */
228 /* Register Masks */
[all …]
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| D | cs42l56.h | 60 /* Device ID and Rev ID Masks */
66 /* Power bit masks */
78 /* serial port and clk masks */
96 /* Class H and misc ctl masks */
112 /* Playback Capture ctl masks */
130 /* Beep masks */
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| D | tas2552.h | 39 /* CFG1 Register Masks */
49 /* CFG2 Register Masks */
57 /* CFG3 Register Masks */
75 /* DOUT Register Masks */
78 /* Serial Interface Control Register Masks */
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| /kernel/linux/linux-5.10/kernel/irq/ |
| D | affinity.c | 45 cpumask_var_t *masks; in alloc_node_to_cpumask() local
48 masks = kcalloc(nr_node_ids, sizeof(cpumask_var_t), GFP_KERNEL); in alloc_node_to_cpumask()
49 if (!masks) in alloc_node_to_cpumask()
53 if (!zalloc_cpumask_var(&masks[node], GFP_KERNEL)) in alloc_node_to_cpumask()
57 return masks; in alloc_node_to_cpumask()
61 free_cpumask_var(masks[node]); in alloc_node_to_cpumask()
62 kfree(masks); in alloc_node_to_cpumask()
66 static void free_node_to_cpumask(cpumask_var_t *masks) in free_node_to_cpumask() argument
71 free_cpumask_var(masks[node]); in free_node_to_cpumask()
72 kfree(masks); in free_node_to_cpumask()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/ezchip/ |
| D | nps_enet.h | 35 /* Tx control register masks and shifts */
43 /* Rx control register masks and shifts */
53 /* Interrupt enable for data buffer events register masks and shifts */
59 /* Gbps Eth MAC Configuration 0 register masks and shifts */
93 /* Gbps Eth MAC Configuration 1 register masks and shifts */
103 /* Gbps Eth MAC Configuration 2 register masks and shifts */
119 /* Gbps Eth MAC Configuration 3 register masks and shifts */
141 /* GE MAC, PCS reset control register masks and shifts */
147 /* Tx phase sync FIFO control register masks and shifts */
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| /kernel/linux/linux-5.10/arch/riscv/mm/ |
| D | pageattr.c | 19 struct pageattr_masks *masks = walk->private; in set_pageattr_masks() local
22 new_val &= ~(pgprot_val(masks->clear_mask)); in set_pageattr_masks()
23 new_val |= (pgprot_val(masks->set_mask)); in set_pageattr_masks()
113 struct pageattr_masks masks = { in __set_memory() local
123 &masks); in __set_memory()
158 struct pageattr_masks masks = { in set_direct_map_invalid_noflush() local
164 ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); in set_direct_map_invalid_noflush()
175 struct pageattr_masks masks = { in set_direct_map_default_noflush() local
181 ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); in set_direct_map_default_noflush()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp_cm.c | 119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
261 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
263 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
265 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
267 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
272 reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; in dpp1_cm_get_reg_field()
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | wakeup-mask.h | 27 * @masks: The list of masks to use.
28 * @nr_masks: The number of entries pointed to buy @masks.
31 * of interrupts and control bits in @masks. We do this at suspend time
36 const struct samsung_wakeup_mask *masks,
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dpp_cm.c | 179 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
181 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
184 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
186 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
188 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
190 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
193 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
195 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
197 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
199 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; in dpp3_gamcor_reg_field()
[all …]
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| D | dcn30_dwb_cm.c | 53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
73 reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in dwb3_get_reg_field_ogam()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_i2c_hw.c | 41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
80 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) in get_channel_status()
82 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) in get_channel_status()
84 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) in get_channel_status()
86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status()
280 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) in set_speed()
600 const struct dce_i2c_mask *masks) in dce_i2c_hw_construct() argument
607 dce_i2c_hw->masks = masks; in dce_i2c_hw_construct()
623 const struct dce_i2c_mask *masks) in dce100_i2c_hw_construct() argument
630 masks); in dce100_i2c_hw_construct()
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/ |
| D | adv7343_regs.h | 92 /* Bit masks for Mode Select Register */
98 /* Bit masks for Mode Register 0 */
103 /* Bit masks for DAC output levels */
106 /* Bit masks for soft reset register */
109 /* Bit masks for HD Mode Register 1 */
131 /* Bit masks for SD Mode Register 1 */
142 /* Bit masks for SD Mode Register 2 */
155 /* Bit masks for HD Mode Register 6 */
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| D | adv7393_regs.h | 100 /* Bit masks for Mode Select Register */
106 /* Bit masks for Mode Register 0 */
111 /* Bit masks for SD brightness/WSS */
115 /* Bit masks for soft reset register */
118 /* Bit masks for HD Mode Register 1 */
140 /* Bit masks for SD Mode Register 1 */
151 /* Bit masks for SD Mode Register 2 */
164 /* Bit masks for HD Mode Register 6 */
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| /kernel/linux/linux-5.10/drivers/media/pci/dt3155/ |
| D | dt3155.h | 69 /* CSR1 bit masks */
88 /* INT_CSR bit masks */
96 /* IIC_CSR1 bit masks */
99 /* IIC_CSR2 bit masks */
105 /* CSR2 bit masks */
115 /* CSR_EVEN/ODD bit masks */
120 /* CONFIG bit masks */
131 /* AD_CMD bit masks */
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| /kernel/linux/linux-5.10/drivers/net/ethernet/intel/ixgb/ |
| D | ixgb_hw.h | 221 /* CTRL0 Bit Masks */
240 /* CTRL1 Bit Masks */
261 /* STATUS Bit Masks */
281 /* EECD Bit Masks */
293 /* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */
307 /* RCTL Bit Masks */
340 /* FCRTL Bit Masks */
343 /* RXDCTL Bit Masks */
351 /* RAIDC Bit Masks */
365 /* RXCSUM Bit Masks */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/uniphier/ |
| D | clk-uniphier-mux.c | 17 const unsigned int *masks; member
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
77 mux->masks = data->masks; in uniphier_clk_register_mux()
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| /kernel/linux/linux-5.10/drivers/usb/gadget/udc/ |
| D | fsl_usb2_udc.h | 115 /* Frame Index Register Bit Masks */
117 /* USB CMD Register Bit Masks */
157 /* USB STS Register Bit Masks */
172 /* USB INTR Register Bit Masks */
183 /* Device Address bit masks */
187 /* endpoint list address bit masks */
190 /* PORTSCX Register Bit Masks */
254 /* otgsc Register Bit Masks */
281 /* USB MODE Register Bit Masks */
294 /* Endpoint Setup Status bit masks */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | tdm-slot.txt | 20 tx and rx masks.
22 For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit
24 the masks.
26 The explicit masks are given as array of integers, where the first
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 166 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
168 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
224 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
226 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
252 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
254 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
256 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
258 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
260 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
262 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
[all …]
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| /kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet.h | 179 /* Bit Masks for Axi Ethernet RAF register */
198 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
203 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
223 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
227 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
231 /* Bit masks for Axi Ethernet RCW1 register */
247 /* Bit masks for Axi Ethernet TC register */
257 /* Bit masks for Axi Ethernet FCC register */
261 /* Bit masks for Axi Ethernet EMMC register */
273 /* Bit masks for Axi Ethernet PHYC register */
[all …]
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| /kernel/linux/linux-5.10/sound/ppc/ |
| D | awacs.h | 29 /* Audio Bit Masks */
32 /* Audio Control Reg Bit Masks */
43 /* Audio Codec Control Reg Bit Masks */
50 /* Audio Codec Control Address Values / Masks */
73 /* Address 0 Bit Masks & Macros */
91 /* Address 1 Bit Masks */
121 /* Address 2 & 4 Bit Masks & Macros */
137 /* Audio Codec Status Reg Bit Masks */
157 /* Clipping Count Reg Bit Masks */
162 /* DBDMA ChannelStatus Bit Masks */
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| /kernel/linux/linux-5.10/drivers/mux/ |
| D | mmio.c | 57 ret = of_property_count_u32_elems(np, "mux-reg-masks"); in mux_mmio_probe()
61 dev_err(dev, "mux-reg-masks property missing or invalid: %d\n", in mux_mmio_probe()
81 ret = of_property_read_u32_index(np, "mux-reg-masks", in mux_mmio_probe()
84 ret = of_property_read_u32_index(np, "mux-reg-masks", in mux_mmio_probe()
87 dev_err(dev, "bitfield %d: failed to read mux-reg-masks property: %d\n", in mux_mmio_probe()
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| /kernel/linux/linux-5.10/include/linux/mfd/ |
| D | rohm-bd70528.h | 139 /* Masks for main IRQ register bits */
224 /* Masks */
307 /* RTC masks to mask out reserved bits */
319 /* WDT masks */
329 /* Charger masks */
345 /* Buck control masks */
357 /* Misc irq masks */
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