Searched +full:reset +full:- +full:names (Results 1 – 25 of 1112) sorted by relevance
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
D | qcom,pcie.txt | 3 - compatible: 7 - "qcom,pcie-ipq8064" for ipq8064 8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 9 - "qcom,pcie-apq8064" for apq8064 10 - "qcom,pcie-apq8084" for apq8084 11 - "qcom,pcie-msm8996" for msm8996 or apq8096 12 - "qcom,pcie-ipq4019" for ipq4019 13 - "qcom,pcie-ipq8074" for ipq8074 14 - "qcom,pcie-qcs404" for qcs404 15 - "qcom,pcie-sdm845" for sdm845 [all …]
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D | amlogic,meson-pcie.txt | 6 Documentation/devicetree/bindings/pci/designware-pcie.txt. 11 - compatible: 13 - "amlogic,axg-pcie" for AXG SoC Family 14 - "amlogic,g12a-pcie" for G12A SoC Family 16 - reg: 18 - reg-names: Must be 19 - "elbi" External local bus interface registers 20 - "cfg" Meson specific registers 21 - "config" PCIe configuration space 22 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. [all …]
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D | hisilicon-histb-pcie.txt | 6 Documentation/devicetree/bindings/pci/designware-pcie.txt. 11 - compatible: Should be one of the following strings: 12 "hisilicon,hi3798cv200-pcie" 13 - reg: Should contain sysctl, rc_dbi, config registers location and length. 14 - reg-names: Must include the following entries: 16 "rc-dbi": configuration space of PCIe controller; 18 - bus-range: PCI bus numbers covered. 19 - interrupts: MSI interrupt. 20 - interrupt-names: Must include "msi" entries. 21 - clocks: List of phandle and clock specifier pairs as listed in clock-names [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/tegra/ |
D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x" 5 - reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10 - interrupts: The interrupt outputs from the controller. 11 - #address-cells: The number of cells used to represent physical base addresses 13 - #size-cells: The number of cells used to represent the size of an address 15 - ranges: The mapping of the host1x address space to the CPU address space. [all …]
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/kernel/linux/linux-5.10/arch/arm/boot/dts/ |
D | tegra20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra20-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra20-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 11 interrupt-parent = <&lic>; 12 #address-cells = <1>; 13 #size-cells = <1>; [all …]
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D | tegra114.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra114-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra114-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 11 interrupt-parent = <&lic>; 12 #address-cells = <1>; 13 #size-cells = <1>; [all …]
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D | tegra30.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra30-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra30-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/soc/tegra-pmc.h> 11 interrupt-parent = <&lic>; 12 #address-cells = <1>; 13 #size-cells = <1>; [all …]
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D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/reset/tegra124-car.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 13 interrupt-parent = <&lic>; [all …]
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D | uniphier-pxs2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 9 #include <dt-bindings/thermal/thermal.h> 12 compatible = "socionext,uniphier-pxs2"; 13 #address-cells = <1>; 14 #size-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 22 compatible = "arm,cortex-a9"; [all …]
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D | uniphier-pro5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 9 compatible = "socionext,uniphier-pro5"; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 #address-cells = <1>; 15 #size-cells = <0>; 19 compatible = "arm,cortex-a9"; 22 enable-method = "psci"; 23 next-level-cache = <&l2>; [all …]
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D | uniphier-pro4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/uniphier-gpio.h> 11 compatible = "socionext,uniphier-pro4"; 12 #address-cells = <1>; 13 #size-cells = <1>; 16 #address-cells = <1>; 17 #size-cells = <0>; 21 compatible = "arm,cortex-a9"; 23 enable-method = "psci"; [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/ |
D | qcom,qmp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 11 - Manu Gautam <mgautam@codeaurora.org> 20 - qcom,ipq8074-qmp-pcie-phy 21 - qcom,ipq8074-qmp-usb3-phy 22 - qcom,msm8996-qmp-pcie-phy 23 - qcom,msm8996-qmp-ufs-phy 24 - qcom,msm8996-qmp-usb3-phy [all …]
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D | allwinner,sun9i-a80-usb-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 14 "#phy-cells": 18 const: allwinner,sun9i-a80-usb-phy 25 - description: Main PHY Clock 27 - items: [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/nvidia/ |
D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra124-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra124-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/thermal/tegra124-soctherm.h> 9 #include <dt-bindings/soc/tegra-pmc.h> 13 interrupt-parent = <&lic>; [all …]
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D | tegra210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra210-car.h> 3 #include <dt-bindings/gpio/tegra-gpio.h> 4 #include <dt-bindings/memory/tegra210-mc.h> 5 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/reset/tegra210-car.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/thermal/tegra124-soctherm.h> 10 #include <dt-bindings/soc/tegra-pmc.h> [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/power/ |
D | amlogic,meson-ee-pwrc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: "http://devicetree.org/schemas/power/amlogic,meson-ee-pwrc.yaml#" 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 8 title: Amlogic Meson Everything-Else Power Domains 11 - Neil Armstrong <narmstrong@baylibre.com> 14 The Everything-Else Power Domains node should be the child of a syscon 17 - compatible: Should be the following: 18 "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon" 26 - amlogic,meson8-pwrc [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/reset/ |
D | uniphier-reset.txt | 1 UniPhier glue reset controller 4 Peripheral core reset in glue layer 5 ----------------------------------- 7 Some peripheral core reset belongs to its own glue layer. Before using 8 this core reset, it is necessary to control the clocks and resets to enable 12 - compatible: Should be 13 "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3 14 "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3 15 "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3 16 "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3 [all …]
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D | reset.txt | 1 = Reset Signal Device Tree Bindings = 3 This binding is intended to represent the hardware reset signals present 4 internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole 8 Hardware blocks typically receive a reset signal. This signal is generated by 9 a reset provider (e.g. power management or clock module) and received by a 10 reset consumer (the module being reset, or a module managing when a sub- 11 ordinate module is reset). This binding exists to represent the provider and 14 A reset signal is represented by the phandle of the provider, plus a reset 15 specifier - a list of DT cells that represents the reset signal within the 16 provider. The length (number of cells) and semantics of the reset specifier [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/amlogic/ |
D | meson-gxbb.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "meson-gx.dtsi" 7 #include "meson-gx-mali450.dtsi" 8 #include <dt-bindings/gpio/meson-gxbb-gpio.h> 9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 10 #include <dt-bindings/clock/gxbb-clkc.h> 11 #include <dt-bindings/clock/gxbb-aoclkc.h> 12 #include <dt-bindings/reset/gxbb-aoclkc.h> 15 compatible = "amlogic,meson-gxbb"; 19 compatible = "amlogic,meson-gxbb-usb2-phy"; [all …]
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D | meson-gxl.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "meson-gx.dtsi" 8 #include <dt-bindings/clock/gxbb-clkc.h> 9 #include <dt-bindings/clock/gxbb-aoclkc.h> 10 #include <dt-bindings/gpio/meson-gxl-gpio.h> 11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 14 compatible = "amlogic,meson-gxl"; 18 compatible = "amlogic,meson-gxl-usb-ctrl"; 21 #address-cells = <2>; 22 #size-cells = <2>; [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpu/ |
D | nvidia,gk20a.txt | 4 - compatible: "nvidia,<gpu>" 6 - nvidia,gk20a 7 - nvidia,gm20b 8 - nvidia,gp10b 9 - nvidia,gv11b 10 - reg: Physical base address and length of the controller's registers. 12 - first entry for bar0 13 - second entry for bar1 14 - interrupts: Must contain an entry for each entry in interrupt-names. 15 See ../interrupt-controller/interrupts.txt for details. [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
D | st,stih4xx.txt | 3 - sti-vtg: video timing generator 5 - compatible: "st,vtg" 6 - reg: Physical base address of the IP registers and length of memory mapped region. 8 - interrupts : VTG interrupt number to the CPU. 9 - st,slave: phandle on a slave vtg 11 - sti-vtac: video timing advanced inter dye communication Rx and TX 13 - compatible: "st,vtac-main" or "st,vtac-aux" 14 - reg: Physical base address of the IP registers and length of memory mapped region. 15 - clocks: from common clock binding: handle hardware IP needed clocks, the 17 See ../clocks/clock-bindings.txt for details. [all …]
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/ |
D | uniphier-pxs3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/thermal/thermal.h> 13 compatible = "socionext,uniphier-pxs3"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <0>; [all …]
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D | uniphier-ld20.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 // Copyright (C) 2015-2016 Socionext Inc. 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/uniphier-gpio.h> 10 #include <dt-bindings/thermal/thermal.h> 13 compatible = "socionext,uniphier-ld20"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 19 #address-cells = <2>; [all …]
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
D | mt8183-afe-pcm.txt | 4 - compatible = "mediatek,mt68183-audio"; 5 - reg: register location and size 6 - interrupts: should contain AFE interrupt 7 - resets: Must contain an entry for each entry in reset-names 8 See ../reset/reset.txt for details. 9 - reset-names: should have these reset names: 11 - power-domains: should define the power domain 12 - clocks: Must contain an entry for each entry in clock-names 13 - clock-names: should have these clock names: 23 afe: mt8183-afe-pcm@11220000 { [all …]
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