/kernel/linux/linux-5.10/Documentation/driver-api/md/ |
D | raid5-cache.rst | 7 caches data to the RAID disks. The cache can be in write-through (supported 8 since 4.4) or write-back mode (supported since 4.10). mdadm (supported since 9 3.4) has a new option '--write-journal' to create array with cache. Please 11 in write-through mode. A user can switch it to write-back mode by:: 13 echo "write-back" > /sys/block/md0/md/journal_mode 15 And switch it back to write-through mode by:: 17 echo "write-through" > /sys/block/md0/md/journal_mode 22 write-through mode 25 This mode mainly fixes the 'write hole' issue. For RAID 4/5/6 array, an unclean 27 and parity don't match. The reason is that a stripe write involves several RAID [all …]
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/kernel/linux/linux-5.10/include/dt-bindings/memory/ |
D | tegra194-mc.h | 149 /* MSS internal memqual MIU7 write clients */ 161 /* High-definition audio (HDA) write clients */ 165 /* SATA write clients */ 171 /* ISP Write client for Crossbar A */ 173 /* ISP Write client Crossbar B */ 177 /* XUSB_HOST write clients */ 181 /* XUSB_DEV write clients */ 189 /* sdmmca memory write client */ 191 /* sdmmc memory write client */ 193 /* sdmmcd memory write client */ [all …]
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D | tegra186-mc.h | 139 /* ISP Write client for Crossbar A */ 141 /* ISP Write client Crossbar B */ 153 /* TSEC Memory Write Client Description */ 167 /* sdmmca memory write client */ 169 /* sdmmcb memory write client */ 171 /* sdmmc memory write client */ 173 /* sdmmcd memory write client */ 177 /* VI Write client */ 189 /* SE Memory Write Client Description */ 197 /* TSECB Memory Write Client Description */ [all …]
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ |
D | armv8-recommended.json | 9 "PublicDescription": "Attributable Level 1 data cache access, write", 12 "BriefDescription": "L1D cache access, write" 21 "PublicDescription": "Attributable Level 1 data cache refill, write", 24 "BriefDescription": "L1D cache refill, write" 39 "PublicDescription": "Attributable Level 1 data cache Write-Back, victim", 42 "BriefDescription": "L1D cache Write-Back, victim" 45 "PublicDescription": "Level 1 data cache Write-Back, cleaning and coherency", 48 "BriefDescription": "L1D cache Write-Back, cleaning and coherency" 63 "PublicDescription": "Attributable Level 1 data TLB refill, write", 66 "BriefDescription": "L1D tlb refill, write" [all …]
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/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
D | regs-uart.h | 12 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ 13 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ 15 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ 16 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ 17 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ 20 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ 21 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ 22 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ 23 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ 28 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ [all …]
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/kernel/linux/linux-5.10/drivers/net/ethernet/aquantia/atlantic/macsec/ |
D | macsec_api.h | 57 /*! Pack the fields of rec, and write the packed data into the 59 * rec - [IN] The bitfield values to write to the table row. 60 * table_index - The table row to write(max 23). 75 /*! Pack the fields of rec, and write the packed data into the 77 * rec - [IN] The bitfield values to write to the table row. 78 * table_index - The table row to write (max 47). 93 /*! Pack the fields of rec, and write the packed data into the 95 * rec - [IN] The bitfield values to write to the table row. 96 * table_index - The table row to write (max 31). 111 /*! Pack the fields of rec, and write the packed data into the [all …]
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
D | uncore-memory.json | 13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 77 …"BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC p… 85 …"BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC p… 102 …"BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB). Derived from unc_m_pm… 105 "EventName": "UNC_M_PMM_BANDWIDTH.WRITE", 143 "BriefDescription": "DRAM Page Activate commands sent due to a write request", 148 …ption": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC… 158 …write on DRAM, so this event increments for every read and write. This event counts whether AutoPr… 168 …write on DRAM, and this event increments for every regular read. This event only counts regular r… 178 …write, on a per channel basis. CAS commands are issued to specify the address to read or write on… [all …]
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/kernel/linux/linux-5.10/Documentation/filesystems/ |
D | zonefs.rst | 12 device support (e.g. f2fs), zonefs does not hide the sequential write 14 write zones of the device must be written sequentially starting from the end 38 conventional zones. Any read or write access can be executed, similarly to a 41 sequentially. Each sequential zone has a write pointer maintained by the 42 device that keeps track of the mandatory start LBA position of the next write 43 to the device. As a result of this write constraint, LBAs in a sequential zone 53 to, for instance, reduce internal write amplification due to garbage collection. 73 information. File sizes come from the device zone type and write pointer 80 state to make it read-only, preventing any data write. 94 For sequential write zones, the sub-directory "seq" is used. [all …]
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/kernel/linux/linux-5.10/arch/mips/kernel/ |
D | cps-vec-ns16550.S | 32 * _mips_cps_putc() - write a character to the UART 33 * @a0: ASCII character to write 45 * _mips_cps_puts() - write a string to the UART 49 * Write a null-terminated ASCII string to the UART. 65 * _mips_cps_putx4 - write a 4b hex value to the UART 66 * @a0: the 4b value to write to the UART 69 * Write a single hexadecimal character to the UART. 82 * _mips_cps_putx8 - write an 8b hex value to the UART 83 * @a0: the 8b value to write to the UART 86 * Write an 8 bit value (ie. 2 hexadecimal characters) to the UART. [all …]
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
D | uncore-memory.json | 13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr", 77 "BriefDescription": "DRAM Page Activate commands sent due to a write request", 82 …ption": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC… 92 …write on DRAM, so this event increments for every read and write. This event counts whether AutoPr… 102 …write on DRAM, and this event increments for every regular read. This event only counts regular r… 112 …write, on a per channel basis. CAS commands are issued to specify the address to read or write on… 117 …AM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", 122 …cDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in… 145 "BriefDescription": "Write Pending Queue Allocations", 150 …Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to… [all …]
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z13/ |
D | extended.json | 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 154 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
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/kernel/linux/linux-5.10/arch/parisc/kernel/ |
D | perf_asm.S | 556 ;* arg1 = 64-bit value to write 586 ; RDR 0 write sequence 588 sync ; RDR 0 write sequence 598 ; RDR 1 write sequence 610 ; RDR 2 write sequence 622 ; RDR 3 write sequence 634 ; RDR 4 write sequence 646 ; RDR 5 write sequence 658 ; RDR 6 write sequence 670 ; RDR 7 write sequence [all …]
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/kernel/linux/linux-5.10/fs/ubifs/ |
D | io.c | 16 * write-buffering support. Write buffers help to save space which otherwise 18 * Instead, data first goes to the write-buffer and is flushed when the 22 * UBIFS distinguishes between minimum write size (@c->min_io_size) and maximum 23 * write size (@c->max_write_size). The latter is the maximum amount of bytes 26 * @c->min_io_size <= @c->max_write_size. Write-buffers are of 28 * write-buffer is flushed, only the portion of it (aligned to @c->min_io_size 29 * boundary) which contains data is written, not the whole write-buffer, 33 * hand, we want to write in optimal @c->max_write_size bytes chunks, which 35 * other hand, we do not want to waste space when synchronizing the write 37 * the next write offset to be not aligned to @c->max_write_size bytes. So the [all …]
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/kernel/linux/linux-5.10/arch/sh/include/asm/ |
D | watchdog.h | 72 * sh_wdt_write_cnt - Write to Counter 73 * @val: Value to write 76 * The upper byte is set manually on each write. 84 * sh_wdt_write_bst - Write to Counter 85 * @val: Value to write 88 * The upper byte is set manually on each write. 105 * sh_wdt_write_csr - Write to Control/Status Register 106 * @val: Value to write 109 * register. The upper byte is set manually on each write. 126 * sh_wdt_write_cnt - Write to Counter [all …]
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z14/ |
D | extended.json | 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 154 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
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/kernel/linux/linux-5.10/arch/s390/kernel/ |
D | module.c | 179 void *(*write)(void *dest, const void *src, size_t len)) in apply_rela_bits() 202 write(dest, &tmp, 1); in apply_rela_bits() 206 write(dest, &tmp, 2); in apply_rela_bits() 209 write(dest, &tmp, 2); in apply_rela_bits() 213 write(dest, &tmp, 4); in apply_rela_bits() 216 write(dest, &tmp, 4); in apply_rela_bits() 219 write(dest, &tmp, 8); in apply_rela_bits() 226 void *(*write)(void *dest, const void *src, size_t len)) in apply_rela() 254 rc = apply_rela_bits(loc, val, 0, 8, 0, write); in apply_rela() 256 rc = apply_rela_bits(loc, val, 0, 12, 0, write); in apply_rela() [all …]
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/kernel/linux/linux-5.10/drivers/crypto/inside-secure/ |
D | safexcel_ring.c | 28 cdr->write = cdr->base; in safexcel_init_ring_descriptors() 65 rdr->write = rdr->base; in safexcel_init_ring_descriptors() 82 void *ptr = ring->write; in safexcel_ring_next_cwptr() 87 if ((ring->write == ring->read - ring->offset) || in safexcel_ring_next_cwptr() 88 (ring->read == ring->base && ring->write == ring->base_end)) in safexcel_ring_next_cwptr() 91 if (ring->write == ring->base_end) { in safexcel_ring_next_cwptr() 92 ring->write = ring->base; in safexcel_ring_next_cwptr() 95 ring->write += ring->offset; in safexcel_ring_next_cwptr() 106 void *ptr = ring->write; in safexcel_ring_next_rwptr() 109 *rtoken = ring->write + ring->shoffset; in safexcel_ring_next_rwptr() [all …]
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/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/ |
D | func-write.rst | 4 .. _func-write: 7 V4L2 write() 13 v4l2-write - Write to a V4L2 device 22 .. c:function:: ssize_t write( int fd, void *buf, size_t count ) 39 :c:func:`write()` writes up to ``count`` bytes to the device 42 enables them. When ``count`` is zero, :c:func:`write()` returns 0 55 variable is set appropriately. In this case the next write will start at 61 available to write the data immediately. 67 The driver does not support multiple write streams and the device is 80 The :c:func:`write()` function is not supported by this driver,
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/kernel/linux/linux-5.10/Documentation/locking/ |
D | seqlock.rst | 24 the end of the write side critical section the sequence count becomes 27 A sequence counter write side critical section must never be preempted 43 multiple writers. Write side critical sections must thus be serialized 46 If the write serialization primitive is not implicitly disabling 48 write side section. If the read section can be invoked from hardirq or 50 disabled before entering the write section. 70 Write path:: 76 /* ... [[write-side critical section]] ... */ 95 As discussed at :ref:`seqcount_t`, sequence count write side critical 98 initialization time, which enables lockdep to validate that the write [all …]
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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/s390/cf_z15/ |
D | extended.json | 7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in… 42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur… 112 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 119 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 126 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 133 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 140 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 147 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… 154 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac… [all …]
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/kernel/linux/linux-5.10/drivers/iio/dac/ |
D | ad5446.c | 40 * @lock: lock to protect the data buffer during write ops 58 * @write: chip specific helper function to write to the register 64 int (*write)(struct ad5446_state *st, unsigned val); member 131 ret = st->chip_info->write(st, val); in ad5446_write_dac_powerdown() 141 .write = ad5446_write_dac_powerdown, 209 ret = st->chip_info->write(st, val); in ad5446_write_raw() 353 .write = ad5446_write, 357 .write = ad5446_write, 361 .write = ad5446_write, 365 .write = ad5446_write, [all …]
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/kernel/linux/linux-5.10/drivers/gpu/drm/i2c/ |
D | tda998x_drv.c | 99 * write a given register, we need to make sure CURPAGE register is set 107 #define REG_CURPAGE 0xff /* write */ 112 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 120 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 123 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 124 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 125 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 129 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 133 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 134 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ [all …]
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/kernel/linux/linux-5.10/kernel/ |
D | sysctl.c | 155 * enum sysctl_writes_mode - supported sysctl write modes 157 * @SYSCTL_WRITES_LEGACY: each write syscall must fully contain the sysctl value 165 * sent to the write syscall. If dealing with strings respect the file 170 * These write modes control how current file position affects the behavior of 171 * updating sysctl values through the proc interface on each write. 206 static int bpf_stats_handler(struct ctl_table *table, int write, in bpf_stats_handler() argument 220 if (write && !capable(CAP_SYS_ADMIN)) in bpf_stats_handler() 225 ret = proc_dointvec_minmax(&tmp, write, buffer, lenp, ppos); in bpf_stats_handler() 226 if (write && !ret && val != saved_val) { in bpf_stats_handler() 241 static int bpf_unpriv_handler(struct ctl_table *table, int write, in bpf_unpriv_handler() argument [all …]
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/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
D | ni_660x.c | 99 [NITIO_G0_INT_ACK] = { 0x004, 2 }, /* write */ 101 [NITIO_G1_INT_ACK] = { 0x006, 2 }, /* write */ 104 [NITIO_G0_CMD] = { 0x00c, 2 }, /* write */ 106 [NITIO_G1_CMD] = { 0x00e, 2 }, /* write */ 109 [NI660X_STC_DIO_OUTPUT] = { 0x014, 2 }, /* write */ 110 [NI660X_STC_DIO_CONTROL] = { 0x016, 2 }, /* write */ 113 [NITIO_G0_MODE] = { 0x034, 2 }, /* write */ 115 [NITIO_G1_MODE] = { 0x036, 2 }, /* write */ 117 [NITIO_G0_LOADA] = { 0x038, 4 }, /* write */ 119 [NITIO_G0_LOADB] = { 0x03c, 4 }, /* write */ [all …]
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/kernel/linux/linux-5.10/Documentation/ABI/testing/ |
D | sysfs-bus-coresight-devices-cti | 67 Description: (RW) Read or write the CTIINEN register selected by inout_sel. 73 Description: (RW) Read or write the CTIOUTEN register selected by inout_sel. 79 Description: (RW) Read or write CTIGATE register. 85 Description: (RW) Read or write ASICCTL register. 91 Description: (Write) Write the INTACK register. 104 Description: (Write) Write APPCLEAR register to deactivate channel. 110 Description: (Write) Write APPPULSE to pulse a channel active for one clock 141 Description: (Write) Attach a CTI input trigger to a CTM channel. 147 Description: (Write) Detach a CTI input trigger from a CTM channel. 153 Description: (Write) Attach a CTI output trigger to a CTM channel. [all …]
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