1 2template = """\ 3/* 4 * Copyright (c) 2019 Valve Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * This file was generated by aco_builder_h.py 26 */ 27 28#ifndef _ACO_BUILDER_ 29#define _ACO_BUILDER_ 30 31#include "aco_ir.h" 32 33namespace aco { 34enum dpp_ctrl { 35 _dpp_quad_perm = 0x000, 36 _dpp_row_sl = 0x100, 37 _dpp_row_sr = 0x110, 38 _dpp_row_rr = 0x120, 39 dpp_wf_sl1 = 0x130, 40 dpp_wf_rl1 = 0x134, 41 dpp_wf_sr1 = 0x138, 42 dpp_wf_rr1 = 0x13C, 43 dpp_row_mirror = 0x140, 44 dpp_row_half_mirror = 0x141, 45 dpp_row_bcast15 = 0x142, 46 dpp_row_bcast31 = 0x143 47}; 48 49inline dpp_ctrl 50dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, unsigned lane3) 51{ 52 assert(lane0 < 4 && lane1 < 4 && lane2 < 4 && lane3 < 4); 53 return (dpp_ctrl)(lane0 | (lane1 << 2) | (lane2 << 4) | (lane3 << 6)); 54} 55 56inline dpp_ctrl 57dpp_row_sl(unsigned amount) 58{ 59 assert(amount > 0 && amount < 16); 60 return (dpp_ctrl)(((unsigned) _dpp_row_sl) | amount); 61} 62 63inline dpp_ctrl 64dpp_row_sr(unsigned amount) 65{ 66 assert(amount > 0 && amount < 16); 67 return (dpp_ctrl)(((unsigned) _dpp_row_sr) | amount); 68} 69 70inline dpp_ctrl 71dpp_row_rr(unsigned amount) 72{ 73 assert(amount > 0 && amount < 16); 74 return (dpp_ctrl)(((unsigned) _dpp_row_rr) | amount); 75} 76 77inline unsigned 78ds_pattern_bitmode(unsigned and_mask, unsigned or_mask, unsigned xor_mask) 79{ 80 assert(and_mask < 32 && or_mask < 32 && xor_mask < 32); 81 return and_mask | (or_mask << 5) | (xor_mask << 10); 82} 83 84aco_ptr<Instruction> create_s_mov(Definition dst, Operand src); 85 86enum sendmsg { 87 sendmsg_none = 0, 88 _sendmsg_gs = 2, 89 _sendmsg_gs_done = 3, 90 sendmsg_save_wave = 4, 91 sendmsg_stall_wave_gen = 5, 92 sendmsg_halt_waves = 6, 93 sendmsg_ordered_ps_done = 7, 94 sendmsg_early_prim_dealloc = 8, 95 sendmsg_gs_alloc_req = 9, 96 sendmsg_id_mask = 0xf, 97}; 98 99inline sendmsg 100sendmsg_gs(bool cut, bool emit, unsigned stream) 101{ 102 assert(stream < 4); 103 return (sendmsg)((unsigned)_sendmsg_gs | (cut << 4) | (emit << 5) | (stream << 8)); 104} 105 106inline sendmsg 107sendmsg_gs_done(bool cut, bool emit, unsigned stream) 108{ 109 assert(stream < 4); 110 return (sendmsg)((unsigned)_sendmsg_gs_done | (cut << 4) | (emit << 5) | (stream << 8)); 111} 112 113class Builder { 114public: 115 struct Result { 116 Instruction *instr; 117 118 Result(Instruction *instr_) : instr(instr_) {} 119 120 operator Instruction *() const { 121 return instr; 122 } 123 124 operator Temp() const { 125 return instr->definitions[0].getTemp(); 126 } 127 128 operator Operand() const { 129 return Operand((Temp)*this); 130 } 131 132 Definition& def(unsigned index) const { 133 return instr->definitions[index]; 134 } 135 136 aco_ptr<Instruction> get_ptr() const { 137 return aco_ptr<Instruction>(instr); 138 } 139 }; 140 141 struct Op { 142 Operand op; 143 Op(Temp tmp) : op(tmp) {} 144 Op(Operand op_) : op(op_) {} 145 Op(Result res) : op((Temp)res) {} 146 }; 147 148 enum WaveSpecificOpcode { 149 s_cselect = (unsigned) aco_opcode::s_cselect_b64, 150 s_cmp_lg = (unsigned) aco_opcode::s_cmp_lg_u64, 151 s_and = (unsigned) aco_opcode::s_and_b64, 152 s_andn2 = (unsigned) aco_opcode::s_andn2_b64, 153 s_or = (unsigned) aco_opcode::s_or_b64, 154 s_orn2 = (unsigned) aco_opcode::s_orn2_b64, 155 s_not = (unsigned) aco_opcode::s_not_b64, 156 s_mov = (unsigned) aco_opcode::s_mov_b64, 157 s_wqm = (unsigned) aco_opcode::s_wqm_b64, 158 s_and_saveexec = (unsigned) aco_opcode::s_and_saveexec_b64, 159 s_or_saveexec = (unsigned) aco_opcode::s_or_saveexec_b64, 160 s_xnor = (unsigned) aco_opcode::s_xnor_b64, 161 s_xor = (unsigned) aco_opcode::s_xor_b64, 162 s_bcnt1_i32 = (unsigned) aco_opcode::s_bcnt1_i32_b64, 163 s_bitcmp1 = (unsigned) aco_opcode::s_bitcmp1_b64, 164 s_ff1_i32 = (unsigned) aco_opcode::s_ff1_i32_b64, 165 s_flbit_i32 = (unsigned) aco_opcode::s_flbit_i32_b64, 166 s_lshl = (unsigned) aco_opcode::s_lshl_b64, 167 }; 168 169 Program *program; 170 bool use_iterator; 171 bool start; // only when use_iterator == false 172 RegClass lm; 173 174 std::vector<aco_ptr<Instruction>> *instructions; 175 std::vector<aco_ptr<Instruction>>::iterator it; 176 bool is_precise = false; 177 bool is_nuw = false; 178 179 Builder(Program *pgm) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(NULL) {} 180 Builder(Program *pgm, Block *block) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(&block->instructions) {} 181 Builder(Program *pgm, std::vector<aco_ptr<Instruction>> *instrs) : program(pgm), use_iterator(false), start(false), lm(pgm ? pgm->lane_mask : s2), instructions(instrs) {} 182 183 Builder precise() const { 184 Builder res = *this; 185 res.is_precise = true; 186 return res; 187 }; 188 189 Builder nuw() const { 190 Builder res = *this; 191 res.is_nuw = true; 192 return res; 193 } 194 195 void moveEnd(Block *block) { 196 instructions = &block->instructions; 197 } 198 199 void reset() { 200 use_iterator = false; 201 start = false; 202 instructions = NULL; 203 } 204 205 void reset(Block *block) { 206 use_iterator = false; 207 start = false; 208 instructions = &block->instructions; 209 } 210 211 void reset(std::vector<aco_ptr<Instruction>> *instrs) { 212 use_iterator = false; 213 start = false; 214 instructions = instrs; 215 } 216 217 void reset(std::vector<aco_ptr<Instruction>> *instrs, std::vector<aco_ptr<Instruction>>::iterator instr_it) { 218 use_iterator = true; 219 start = false; 220 instructions = instrs; 221 it = instr_it; 222 } 223 224 Result insert(aco_ptr<Instruction> instr) { 225 Instruction *instr_ptr = instr.get(); 226 if (instructions) { 227 if (use_iterator) { 228 it = instructions->emplace(it, std::move(instr)); 229 it = std::next(it); 230 } else if (!start) { 231 instructions->emplace_back(std::move(instr)); 232 } else { 233 instructions->emplace(instructions->begin(), std::move(instr)); 234 } 235 } 236 return Result(instr_ptr); 237 } 238 239 Result insert(Instruction* instr) { 240 if (instructions) { 241 if (use_iterator) { 242 it = instructions->emplace(it, aco_ptr<Instruction>(instr)); 243 it = std::next(it); 244 } else if (!start) { 245 instructions->emplace_back(aco_ptr<Instruction>(instr)); 246 } else { 247 instructions->emplace(instructions->begin(), aco_ptr<Instruction>(instr)); 248 } 249 } 250 return Result(instr); 251 } 252 253 Temp tmp(RegClass rc) { 254 return program->allocateTmp(rc); 255 } 256 257 Temp tmp(RegType type, unsigned size) { 258 return tmp(RegClass(type, size)); 259 } 260 261 Definition def(RegClass rc) { 262 return Definition(program->allocateTmp(rc)); 263 } 264 265 Definition def(RegType type, unsigned size) { 266 return def(RegClass(type, size)); 267 } 268 269 Definition def(RegClass rc, PhysReg reg) { 270 return Definition(program->allocateId(rc), reg, rc); 271 } 272 273 inline aco_opcode w64or32(WaveSpecificOpcode opcode) const { 274 if (program->wave_size == 64) 275 return (aco_opcode) opcode; 276 277 switch (opcode) { 278 case s_cselect: 279 return aco_opcode::s_cselect_b32; 280 case s_cmp_lg: 281 return aco_opcode::s_cmp_lg_u32; 282 case s_and: 283 return aco_opcode::s_and_b32; 284 case s_andn2: 285 return aco_opcode::s_andn2_b32; 286 case s_or: 287 return aco_opcode::s_or_b32; 288 case s_orn2: 289 return aco_opcode::s_orn2_b32; 290 case s_not: 291 return aco_opcode::s_not_b32; 292 case s_mov: 293 return aco_opcode::s_mov_b32; 294 case s_wqm: 295 return aco_opcode::s_wqm_b32; 296 case s_and_saveexec: 297 return aco_opcode::s_and_saveexec_b32; 298 case s_or_saveexec: 299 return aco_opcode::s_or_saveexec_b32; 300 case s_xnor: 301 return aco_opcode::s_xnor_b32; 302 case s_xor: 303 return aco_opcode::s_xor_b32; 304 case s_bcnt1_i32: 305 return aco_opcode::s_bcnt1_i32_b32; 306 case s_bitcmp1: 307 return aco_opcode::s_bitcmp1_b32; 308 case s_ff1_i32: 309 return aco_opcode::s_ff1_i32_b32; 310 case s_flbit_i32: 311 return aco_opcode::s_flbit_i32_b32; 312 case s_lshl: 313 return aco_opcode::s_lshl_b32; 314 default: 315 unreachable("Unsupported wave specific opcode."); 316 } 317 } 318 319% for fixed in ['m0', 'vcc', 'exec', 'scc']: 320 Operand ${fixed}(Temp tmp) { 321 % if fixed == 'vcc' or fixed == 'exec': 322 //vcc_hi and exec_hi can still be used in wave32 323 assert(tmp.type() == RegType::sgpr && tmp.bytes() <= 8); 324 % endif 325 Operand op(tmp); 326 op.setFixed(aco::${fixed}); 327 return op; 328 } 329 330 Definition ${fixed}(Definition def) { 331 % if fixed == 'vcc' or fixed == 'exec': 332 //vcc_hi and exec_hi can still be used in wave32 333 assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8); 334 % endif 335 def.setFixed(aco::${fixed}); 336 return def; 337 } 338 339 Definition hint_${fixed}(Definition def) { 340 % if fixed == 'vcc' or fixed == 'exec': 341 //vcc_hi and exec_hi can still be used in wave32 342 assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8); 343 % endif 344 def.setHint(aco::${fixed}); 345 return def; 346 } 347 348 Definition hint_${fixed}(RegClass rc) { 349 return hint_${fixed}(def(rc)); 350 } 351 352% endfor 353 354 Operand set16bit(Operand op) { 355 op.set16bit(true); 356 return op; 357 } 358 359 Operand set24bit(Operand op) { 360 op.set24bit(true); 361 return op; 362 } 363 364 /* hand-written helpers */ 365 Temp as_uniform(Op op) 366 { 367 assert(op.op.isTemp()); 368 if (op.op.getTemp().type() == RegType::vgpr) 369 return pseudo(aco_opcode::p_as_uniform, def(RegType::sgpr, op.op.size()), op); 370 else 371 return op.op.getTemp(); 372 } 373 374 Result v_mul_imm(Definition dst, Temp tmp, uint32_t imm, bool bits24=false) 375 { 376 assert(tmp.type() == RegType::vgpr); 377 bool has_lshl_add = program->chip_class >= GFX9; 378 /* v_mul_lo_u32 has 1.6x the latency of most VALU on GFX10 (8 vs 5 cycles), 379 * compared to 4x the latency on <GFX10. */ 380 unsigned mul_cost = program->chip_class >= GFX10 ? 1 : (4 + Operand::c32(imm).isLiteral()); 381 if (imm == 0) { 382 return copy(dst, Operand::zero()); 383 } else if (imm == 1) { 384 return copy(dst, Operand(tmp)); 385 } else if (util_is_power_of_two_or_zero(imm)) { 386 return vop2(aco_opcode::v_lshlrev_b32, dst, Operand::c32(ffs(imm) - 1u), tmp); 387 } else if (bits24) { 388 return vop2(aco_opcode::v_mul_u32_u24, dst, Operand::c32(imm), tmp); 389 } else if (util_is_power_of_two_nonzero(imm - 1u)) { 390 return vadd32(dst, vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(ffs(imm - 1u) - 1u), tmp), tmp); 391 } else if (mul_cost > 2 && util_is_power_of_two_nonzero(imm + 1u)) { 392 return vsub32(dst, vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(ffs(imm + 1u) - 1u), tmp), tmp); 393 } 394 395 unsigned instrs_required = util_bitcount(imm); 396 if (!has_lshl_add) { 397 instrs_required = util_bitcount(imm) - (imm & 0x1); /* shifts */ 398 instrs_required += util_bitcount(imm) - 1; /* additions */ 399 } 400 if (instrs_required < mul_cost) { 401 Result res(NULL); 402 Temp cur; 403 while (imm) { 404 unsigned shift = u_bit_scan(&imm); 405 Definition tmp_dst = imm ? def(v1) : dst; 406 407 if (shift && cur.id()) 408 res = vadd32(Definition(tmp_dst), vop2(aco_opcode::v_lshlrev_b32, def(v1), Operand::c32(shift), tmp), cur); 409 else if (shift) 410 res = vop2(aco_opcode::v_lshlrev_b32, Definition(tmp_dst), Operand::c32(shift), tmp); 411 else if (cur.id()) 412 res = vadd32(Definition(tmp_dst), tmp, cur); 413 else 414 tmp_dst = Definition(tmp); 415 416 cur = tmp_dst.getTemp(); 417 } 418 return res; 419 } 420 421 Temp imm_tmp = copy(def(s1), Operand::c32(imm)); 422 return vop3(aco_opcode::v_mul_lo_u32, dst, imm_tmp, tmp); 423 } 424 425 Result v_mul24_imm(Definition dst, Temp tmp, uint32_t imm) 426 { 427 return v_mul_imm(dst, tmp, imm, true); 428 } 429 430 Result copy(Definition dst, Op op) { 431 return pseudo(aco_opcode::p_parallelcopy, dst, op); 432 } 433 434 Result vadd32(Definition dst, Op a, Op b, bool carry_out=false, Op carry_in=Op(Operand(s2)), bool post_ra=false) { 435 if (b.op.isConstant() || b.op.regClass().type() != RegType::vgpr) 436 std::swap(a, b); 437 if (!post_ra && (!b.op.hasRegClass() || b.op.regClass().type() == RegType::sgpr)) 438 b = copy(def(v1), b); 439 440 if (!carry_in.op.isUndefined()) 441 return vop2(aco_opcode::v_addc_co_u32, Definition(dst), hint_vcc(def(lm)), a, b, carry_in); 442 else if (program->chip_class >= GFX10 && carry_out) 443 return vop3(aco_opcode::v_add_co_u32_e64, Definition(dst), def(lm), a, b); 444 else if (program->chip_class < GFX9 || carry_out) 445 return vop2(aco_opcode::v_add_co_u32, Definition(dst), hint_vcc(def(lm)), a, b); 446 else 447 return vop2(aco_opcode::v_add_u32, Definition(dst), a, b); 448 } 449 450 Result vsub32(Definition dst, Op a, Op b, bool carry_out=false, Op borrow=Op(Operand(s2))) 451 { 452 if (!borrow.op.isUndefined() || program->chip_class < GFX9) 453 carry_out = true; 454 455 bool reverse = !b.op.isTemp() || b.op.regClass().type() != RegType::vgpr; 456 if (reverse) 457 std::swap(a, b); 458 if (!b.op.hasRegClass() || b.op.regClass().type() == RegType::sgpr) 459 b = copy(def(v1), b); 460 461 aco_opcode op; 462 Temp carry; 463 if (carry_out) { 464 carry = tmp(s2); 465 if (borrow.op.isUndefined()) 466 op = reverse ? aco_opcode::v_subrev_co_u32 : aco_opcode::v_sub_co_u32; 467 else 468 op = reverse ? aco_opcode::v_subbrev_co_u32 : aco_opcode::v_subb_co_u32; 469 } else { 470 op = reverse ? aco_opcode::v_subrev_u32 : aco_opcode::v_sub_u32; 471 } 472 bool vop3 = false; 473 if (program->chip_class >= GFX10 && op == aco_opcode::v_subrev_co_u32) { 474 vop3 = true; 475 op = aco_opcode::v_subrev_co_u32_e64; 476 } else if (program->chip_class >= GFX10 && op == aco_opcode::v_sub_co_u32) { 477 vop3 = true; 478 op = aco_opcode::v_sub_co_u32_e64; 479 } 480 481 int num_ops = borrow.op.isUndefined() ? 2 : 3; 482 int num_defs = carry_out ? 2 : 1; 483 aco_ptr<Instruction> sub; 484 if (vop3) 485 sub.reset(create_instruction<VOP3_instruction>(op, Format::VOP3, num_ops, num_defs)); 486 else 487 sub.reset(create_instruction<VOP2_instruction>(op, Format::VOP2, num_ops, num_defs)); 488 sub->operands[0] = a.op; 489 sub->operands[1] = b.op; 490 if (!borrow.op.isUndefined()) 491 sub->operands[2] = borrow.op; 492 sub->definitions[0] = dst; 493 if (carry_out) { 494 sub->definitions[1] = Definition(carry); 495 sub->definitions[1].setHint(aco::vcc); 496 } 497 return insert(std::move(sub)); 498 } 499 500 Result readlane(Definition dst, Op vsrc, Op lane) 501 { 502 if (program->chip_class >= GFX8) 503 return vop3(aco_opcode::v_readlane_b32_e64, dst, vsrc, lane); 504 else 505 return vop2(aco_opcode::v_readlane_b32, dst, vsrc, lane); 506 } 507 Result writelane(Definition dst, Op val, Op lane, Op vsrc) { 508 if (program->chip_class >= GFX8) 509 return vop3(aco_opcode::v_writelane_b32_e64, dst, val, lane, vsrc); 510 else 511 return vop2(aco_opcode::v_writelane_b32, dst, val, lane, vsrc); 512 } 513<% 514import itertools 515formats = [("pseudo", [Format.PSEUDO], 'Pseudo_instruction', list(itertools.product(range(5), range(6))) + [(8, 1), (1, 8)]), 516 ("sop1", [Format.SOP1], 'SOP1_instruction', [(0, 1), (1, 0), (1, 1), (2, 1), (3, 2)]), 517 ("sop2", [Format.SOP2], 'SOP2_instruction', itertools.product([1, 2], [2, 3])), 518 ("sopk", [Format.SOPK], 'SOPK_instruction', itertools.product([0, 1, 2], [0, 1])), 519 ("sopp", [Format.SOPP], 'SOPP_instruction', itertools.product([0, 1], [0, 1])), 520 ("sopc", [Format.SOPC], 'SOPC_instruction', [(1, 2)]), 521 ("smem", [Format.SMEM], 'SMEM_instruction', [(0, 4), (0, 3), (1, 0), (1, 3), (1, 2), (0, 0)]), 522 ("ds", [Format.DS], 'DS_instruction', [(1, 1), (1, 2), (0, 3), (0, 4)]), 523 ("mubuf", [Format.MUBUF], 'MUBUF_instruction', [(0, 4), (1, 3)]), 524 ("mtbuf", [Format.MTBUF], 'MTBUF_instruction', [(0, 4), (1, 3)]), 525 ("mimg", [Format.MIMG], 'MIMG_instruction', itertools.product([0, 1], [3, 4, 5, 6, 7])), 526 ("exp", [Format.EXP], 'Export_instruction', [(0, 4)]), 527 ("branch", [Format.PSEUDO_BRANCH], 'Pseudo_branch_instruction', itertools.product([1], [0, 1])), 528 ("barrier", [Format.PSEUDO_BARRIER], 'Pseudo_barrier_instruction', [(0, 0)]), 529 ("reduction", [Format.PSEUDO_REDUCTION], 'Pseudo_reduction_instruction', [(3, 2)]), 530 ("vop1", [Format.VOP1], 'VOP1_instruction', [(0, 0), (1, 1), (2, 2)]), 531 ("vop1_sdwa", [Format.VOP1, Format.SDWA], 'SDWA_instruction', [(1, 1)]), 532 ("vop2", [Format.VOP2], 'VOP2_instruction', itertools.product([1, 2], [2, 3])), 533 ("vop2_sdwa", [Format.VOP2, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2, 3])), 534 ("vopc", [Format.VOPC], 'VOPC_instruction', itertools.product([1, 2], [2])), 535 ("vopc_sdwa", [Format.VOPC, Format.SDWA], 'SDWA_instruction', itertools.product([1, 2], [2])), 536 ("vop3", [Format.VOP3], 'VOP3_instruction', [(1, 3), (1, 2), (1, 1), (2, 2)]), 537 ("vop3p", [Format.VOP3P], 'VOP3P_instruction', [(1, 2), (1, 3)]), 538 ("vintrp", [Format.VINTRP], 'Interp_instruction', [(1, 2), (1, 3)]), 539 ("vop1_dpp", [Format.VOP1, Format.DPP], 'DPP_instruction', [(1, 1)]), 540 ("vop2_dpp", [Format.VOP2, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2, 3])), 541 ("vopc_dpp", [Format.VOPC, Format.DPP], 'DPP_instruction', itertools.product([1, 2], [2])), 542 ("vop1_e64", [Format.VOP1, Format.VOP3], 'VOP3_instruction', itertools.product([1], [1])), 543 ("vop2_e64", [Format.VOP2, Format.VOP3], 'VOP3_instruction', itertools.product([1, 2], [2, 3])), 544 ("vopc_e64", [Format.VOPC, Format.VOP3], 'VOP3_instruction', itertools.product([1, 2], [2])), 545 ("flat", [Format.FLAT], 'FLAT_instruction', [(0, 3), (1, 2)]), 546 ("global", [Format.GLOBAL], 'FLAT_instruction', [(0, 3), (1, 2)])] 547formats = [(f if len(f) == 5 else f + ('',)) for f in formats] 548%>\\ 549% for name, formats, struct, shapes, extra_field_setup in formats: 550 % for num_definitions, num_operands in shapes: 551 <% 552 args = ['aco_opcode opcode'] 553 for i in range(num_definitions): 554 args.append('Definition def%d' % i) 555 for i in range(num_operands): 556 args.append('Op op%d' % i) 557 for f in formats: 558 args += f.get_builder_field_decls() 559 %>\\ 560 561 Result ${name}(${', '.join(args)}) 562 { 563 ${struct} *instr = create_instruction<${struct}>(opcode, (Format)(${'|'.join('(int)Format::%s' % f.name for f in formats)}), ${num_operands}, ${num_definitions}); 564 % for i in range(num_definitions): 565 instr->definitions[${i}] = def${i}; 566 instr->definitions[${i}].setPrecise(is_precise); 567 instr->definitions[${i}].setNUW(is_nuw); 568 % endfor 569 % for i in range(num_operands): 570 instr->operands[${i}] = op${i}.op; 571 % endfor 572 % for f in formats: 573 % for dest, field_name in zip(f.get_builder_field_dests(), f.get_builder_field_names()): 574 instr->${dest} = ${field_name}; 575 % endfor 576 ${f.get_builder_initialization(num_operands)} 577 % endfor 578 ${extra_field_setup} 579 return insert(instr); 580 } 581 582 % if name == 'sop1' or name == 'sop2' or name == 'sopc': 583 <% 584 args[0] = 'WaveSpecificOpcode opcode' 585 params = [] 586 for i in range(num_definitions): 587 params.append('def%d' % i) 588 for i in range(num_operands): 589 params.append('op%d' % i) 590 %>\\ 591 592 inline Result ${name}(${', '.join(args)}) 593 { 594 return ${name}(w64or32(opcode), ${', '.join(params)}); 595 } 596 597 % endif 598 % endfor 599% endfor 600}; 601 602} // namespace aco 603 604#endif /* _ACO_BUILDER_ */""" 605 606from aco_opcodes import opcodes, Format 607from mako.template import Template 608 609print(Template(template).render(opcodes=opcodes, Format=Format)) 610