1 /* 2 * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 /****************************************************************************** 17 * @file dw_timer.h 18 * @brief header file for timer driver 19 * @version V1.0 20 * @date 02. June 2017 21 ******************************************************************************/ 22 #ifndef __DW_TIMER_H 23 #define __DW_TIMER_H 24 25 #include <stdio.h> 26 #include "soc.h" 27 28 /* 29 * define the bits for TxControl 30 */ 31 #define DW_TIMER_TXCONTROL_ENABLE (1UL << 0) 32 #define DW_TIMER_TXCONTROL_MODE (1UL << 1) 33 #define DW_TIMER_TXCONTROL_INTMASK (1UL << 2) 34 35 #define DW_TIMER_INIT_DEFAULT_VALUE (0xffffffff / drv_get_sys_freq() * 1000000) 36 37 typedef struct { 38 __IOM uint32_t TxLoadCount; /* Offset: 0x000 (R/W) Receive buffer register */ 39 __IM uint32_t TxCurrentValue; /* Offset: 0x004 (R) Transmission hold register */ 40 __IOM uint8_t TxControl: 4; /* Offset: 0x008 (R/W) Clock frequency division low section register */ 41 uint8_t RESERVED0[3]; 42 __IM uint8_t TxEOI: 1; /* Offset: 0x00c (R) Clock frequency division high section register */ 43 uint8_t RESERVED1[3]; 44 __IM uint8_t TxIntStatus: 1; /* Offset: 0x010 (R) Interrupt enable register */ 45 uint8_t RESERVED2[3]; 46 } dw_timer_reg_t; 47 48 #endif /* __DW_TIMER_H */ 49