1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 4 * 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <Mingkai.hu@freescale.com> 9 */ 10 11#include <dt-bindings/thermal/thermal.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "fsl,ls1043a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 fman0 = &fman0; 23 ethernet0 = &enet0; 24 ethernet1 = &enet1; 25 ethernet2 = &enet2; 26 ethernet3 = &enet3; 27 ethernet4 = &enet4; 28 ethernet5 = &enet5; 29 ethernet6 = &enet6; 30 rtc1 = &ftm_alarm0; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 /* 38 * We expect the enable-method for cpu's to be "psci", but this 39 * is dependent on the SoC FW, which will fill this in. 40 * 41 * Currently supported enable-method is psci v0.2 42 */ 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x0>; 47 clocks = <&clockgen 1 0>; 48 next-level-cache = <&l2>; 49 cpu-idle-states = <&CPU_PH20>; 50 #cooling-cells = <2>; 51 }; 52 53 cpu1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x1>; 57 clocks = <&clockgen 1 0>; 58 next-level-cache = <&l2>; 59 cpu-idle-states = <&CPU_PH20>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu2: cpu@2 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x2>; 67 clocks = <&clockgen 1 0>; 68 next-level-cache = <&l2>; 69 cpu-idle-states = <&CPU_PH20>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x3>; 77 clocks = <&clockgen 1 0>; 78 next-level-cache = <&l2>; 79 cpu-idle-states = <&CPU_PH20>; 80 #cooling-cells = <2>; 81 }; 82 83 l2: l2-cache { 84 compatible = "cache"; 85 }; 86 }; 87 88 idle-states { 89 /* 90 * PSCI node is not added default, U-boot will add missing 91 * parts if it determines to use PSCI. 92 */ 93 entry-method = "psci"; 94 95 CPU_PH20: cpu-ph20 { 96 compatible = "arm,idle-state"; 97 idle-state-name = "PH20"; 98 arm,psci-suspend-param = <0x0>; 99 entry-latency-us = <1000>; 100 exit-latency-us = <1000>; 101 min-residency-us = <3000>; 102 }; 103 }; 104 105 memory@80000000 { 106 device_type = "memory"; 107 reg = <0x0 0x80000000 0 0x80000000>; 108 /* DRAM space 1, size: 2GiB DRAM */ 109 }; 110 111 reserved-memory { 112 #address-cells = <2>; 113 #size-cells = <2>; 114 ranges; 115 116 bman_fbpr: bman-fbpr { 117 compatible = "shared-dma-pool"; 118 size = <0 0x1000000>; 119 alignment = <0 0x1000000>; 120 no-map; 121 }; 122 123 qman_fqd: qman-fqd { 124 compatible = "shared-dma-pool"; 125 size = <0 0x400000>; 126 alignment = <0 0x400000>; 127 no-map; 128 }; 129 130 qman_pfdr: qman-pfdr { 131 compatible = "shared-dma-pool"; 132 size = <0 0x2000000>; 133 alignment = <0 0x2000000>; 134 no-map; 135 }; 136 }; 137 138 sysclk: sysclk { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 clock-frequency = <100000000>; 142 clock-output-names = "sysclk"; 143 }; 144 145 reboot { 146 compatible ="syscon-reboot"; 147 regmap = <&dcfg>; 148 offset = <0xb0>; 149 mask = <0x02>; 150 }; 151 152 thermal-zones { 153 ddr-controller { 154 polling-delay-passive = <1000>; 155 polling-delay = <5000>; 156 thermal-sensors = <&tmu 0>; 157 158 trips { 159 ddr-ctrler-alert { 160 temperature = <85000>; 161 hysteresis = <2000>; 162 type = "passive"; 163 }; 164 165 ddr-ctrler-crit { 166 temperature = <95000>; 167 hysteresis = <2000>; 168 type = "critical"; 169 }; 170 }; 171 }; 172 173 serdes { 174 polling-delay-passive = <1000>; 175 polling-delay = <5000>; 176 thermal-sensors = <&tmu 1>; 177 178 trips { 179 serdes-alert { 180 temperature = <85000>; 181 hysteresis = <2000>; 182 type = "passive"; 183 }; 184 185 serdes-crit { 186 temperature = <95000>; 187 hysteresis = <2000>; 188 type = "critical"; 189 }; 190 }; 191 }; 192 193 fman { 194 polling-delay-passive = <1000>; 195 polling-delay = <5000>; 196 thermal-sensors = <&tmu 2>; 197 198 trips { 199 fman-alert { 200 temperature = <85000>; 201 hysteresis = <2000>; 202 type = "passive"; 203 }; 204 205 fman-crit { 206 temperature = <95000>; 207 hysteresis = <2000>; 208 type = "critical"; 209 }; 210 }; 211 }; 212 213 core-cluster { 214 polling-delay-passive = <1000>; 215 polling-delay = <5000>; 216 thermal-sensors = <&tmu 3>; 217 218 trips { 219 core_cluster_alert: core-cluster-alert { 220 temperature = <85000>; 221 hysteresis = <2000>; 222 type = "passive"; 223 }; 224 225 core_cluster_crit: core-cluster-crit { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 232 cooling-maps { 233 map0 { 234 trip = <&core_cluster_alert>; 235 cooling-device = 236 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 237 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 238 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 239 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 240 }; 241 }; 242 }; 243 244 sec { 245 polling-delay-passive = <1000>; 246 polling-delay = <5000>; 247 thermal-sensors = <&tmu 4>; 248 249 trips { 250 sec-alert { 251 temperature = <85000>; 252 hysteresis = <2000>; 253 type = "passive"; 254 }; 255 256 sec-crit { 257 temperature = <95000>; 258 hysteresis = <2000>; 259 type = "critical"; 260 }; 261 }; 262 }; 263 }; 264 265 timer { 266 compatible = "arm,armv8-timer"; 267 interrupts = <1 13 0xf08>, /* Physical Secure PPI */ 268 <1 14 0xf08>, /* Physical Non-Secure PPI */ 269 <1 11 0xf08>, /* Virtual PPI */ 270 <1 10 0xf08>; /* Hypervisor PPI */ 271 fsl,erratum-a008585; 272 }; 273 274 pmu { 275 compatible = "arm,armv8-pmuv3"; 276 interrupts = <0 106 0x4>, 277 <0 107 0x4>, 278 <0 95 0x4>, 279 <0 97 0x4>; 280 interrupt-affinity = <&cpu0>, 281 <&cpu1>, 282 <&cpu2>, 283 <&cpu3>; 284 }; 285 286 gic: interrupt-controller@1400000 { 287 compatible = "arm,gic-400"; 288 #interrupt-cells = <3>; 289 interrupt-controller; 290 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 291 <0x0 0x1402000 0 0x2000>, /* GICC */ 292 <0x0 0x1404000 0 0x2000>, /* GICH */ 293 <0x0 0x1406000 0 0x2000>; /* GICV */ 294 interrupts = <1 9 0xf08>; 295 }; 296 297 soc: soc { 298 compatible = "simple-bus"; 299 #address-cells = <2>; 300 #size-cells = <2>; 301 ranges; 302 303 clockgen: clocking@1ee1000 { 304 compatible = "fsl,ls1043a-clockgen"; 305 reg = <0x0 0x1ee1000 0x0 0x1000>; 306 #clock-cells = <2>; 307 clocks = <&sysclk>; 308 }; 309 310 scfg: scfg@1570000 { 311 compatible = "fsl,ls1043a-scfg", "syscon"; 312 reg = <0x0 0x1570000 0x0 0x10000>; 313 big-endian; 314 }; 315 316 crypto: crypto@1700000 { 317 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 318 "fsl,sec-v4.0"; 319 fsl,sec-era = <3>; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges = <0x0 0x00 0x1700000 0x100000>; 323 reg = <0x00 0x1700000 0x0 0x100000>; 324 interrupts = <0 75 0x4>; 325 dma-coherent; 326 327 sec_jr0: jr@10000 { 328 compatible = "fsl,sec-v5.4-job-ring", 329 "fsl,sec-v5.0-job-ring", 330 "fsl,sec-v4.0-job-ring"; 331 reg = <0x10000 0x10000>; 332 interrupts = <0 71 0x4>; 333 }; 334 335 sec_jr1: jr@20000 { 336 compatible = "fsl,sec-v5.4-job-ring", 337 "fsl,sec-v5.0-job-ring", 338 "fsl,sec-v4.0-job-ring"; 339 reg = <0x20000 0x10000>; 340 interrupts = <0 72 0x4>; 341 }; 342 343 sec_jr2: jr@30000 { 344 compatible = "fsl,sec-v5.4-job-ring", 345 "fsl,sec-v5.0-job-ring", 346 "fsl,sec-v4.0-job-ring"; 347 reg = <0x30000 0x10000>; 348 interrupts = <0 73 0x4>; 349 }; 350 351 sec_jr3: jr@40000 { 352 compatible = "fsl,sec-v5.4-job-ring", 353 "fsl,sec-v5.0-job-ring", 354 "fsl,sec-v4.0-job-ring"; 355 reg = <0x40000 0x10000>; 356 interrupts = <0 74 0x4>; 357 }; 358 }; 359 360 dcfg: dcfg@1ee0000 { 361 compatible = "fsl,ls1043a-dcfg", "syscon"; 362 reg = <0x0 0x1ee0000 0x0 0x10000>; 363 big-endian; 364 }; 365 366 ifc: ifc@1530000 { 367 compatible = "fsl,ifc", "simple-bus"; 368 reg = <0x0 0x1530000 0x0 0x10000>; 369 interrupts = <0 43 0x4>; 370 }; 371 372 qspi: spi@1550000 { 373 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 reg = <0x0 0x1550000 0x0 0x10000>, 377 <0x0 0x40000000 0x0 0x4000000>; 378 reg-names = "QuadSPI", "QuadSPI-memory"; 379 interrupts = <0 99 0x4>; 380 clock-names = "qspi_en", "qspi"; 381 clocks = <&clockgen 4 0>, <&clockgen 4 0>; 382 status = "disabled"; 383 }; 384 385 esdhc: esdhc@1560000 { 386 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 387 reg = <0x0 0x1560000 0x0 0x10000>; 388 interrupts = <0 62 0x4>; 389 clock-frequency = <0>; 390 voltage-ranges = <1800 1800 3300 3300>; 391 sdhci,auto-cmd12; 392 big-endian; 393 bus-width = <4>; 394 }; 395 396 ddr: memory-controller@1080000 { 397 compatible = "fsl,qoriq-memory-controller"; 398 reg = <0x0 0x1080000 0x0 0x1000>; 399 interrupts = <0 144 0x4>; 400 big-endian; 401 }; 402 403 tmu: tmu@1f00000 { 404 compatible = "fsl,qoriq-tmu"; 405 reg = <0x0 0x1f00000 0x0 0x10000>; 406 interrupts = <0 33 0x4>; 407 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 408 fsl,tmu-calibration = <0x00000000 0x00000026 409 0x00000001 0x0000002d 410 0x00000002 0x00000032 411 0x00000003 0x00000039 412 0x00000004 0x0000003f 413 0x00000005 0x00000046 414 0x00000006 0x0000004d 415 0x00000007 0x00000054 416 0x00000008 0x0000005a 417 0x00000009 0x00000061 418 0x0000000a 0x0000006a 419 0x0000000b 0x00000071 420 421 0x00010000 0x00000025 422 0x00010001 0x0000002c 423 0x00010002 0x00000035 424 0x00010003 0x0000003d 425 0x00010004 0x00000045 426 0x00010005 0x0000004e 427 0x00010006 0x00000057 428 0x00010007 0x00000061 429 0x00010008 0x0000006b 430 0x00010009 0x00000076 431 432 0x00020000 0x00000029 433 0x00020001 0x00000033 434 0x00020002 0x0000003d 435 0x00020003 0x00000049 436 0x00020004 0x00000056 437 0x00020005 0x00000061 438 0x00020006 0x0000006d 439 440 0x00030000 0x00000021 441 0x00030001 0x0000002a 442 0x00030002 0x0000003c 443 0x00030003 0x0000004e>; 444 #thermal-sensor-cells = <1>; 445 }; 446 447 qman: qman@1880000 { 448 compatible = "fsl,qman"; 449 reg = <0x0 0x1880000 0x0 0x10000>; 450 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 451 memory-region = <&qman_fqd &qman_pfdr>; 452 }; 453 454 bman: bman@1890000 { 455 compatible = "fsl,bman"; 456 reg = <0x0 0x1890000 0x0 0x10000>; 457 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 458 memory-region = <&bman_fbpr>; 459 }; 460 461 bportals: bman-portals@508000000 { 462 ranges = <0x0 0x5 0x08000000 0x8000000>; 463 }; 464 465 qportals: qman-portals@500000000 { 466 ranges = <0x0 0x5 0x00000000 0x8000000>; 467 }; 468 469 dspi0: spi@2100000 { 470 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 reg = <0x0 0x2100000 0x0 0x10000>; 474 interrupts = <0 64 0x4>; 475 clock-names = "dspi"; 476 clocks = <&clockgen 4 0>; 477 spi-num-chipselects = <5>; 478 big-endian; 479 status = "disabled"; 480 }; 481 482 dspi1: spi@2110000 { 483 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 reg = <0x0 0x2110000 0x0 0x10000>; 487 interrupts = <0 65 0x4>; 488 clock-names = "dspi"; 489 clocks = <&clockgen 4 0>; 490 spi-num-chipselects = <5>; 491 big-endian; 492 status = "disabled"; 493 }; 494 495 i2c0: i2c@2180000 { 496 compatible = "fsl,vf610-i2c"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 reg = <0x0 0x2180000 0x0 0x10000>; 500 interrupts = <0 56 0x4>; 501 clock-names = "i2c"; 502 clocks = <&clockgen 4 0>; 503 dmas = <&edma0 1 39>, 504 <&edma0 1 38>; 505 dma-names = "tx", "rx"; 506 status = "disabled"; 507 }; 508 509 i2c1: i2c@2190000 { 510 compatible = "fsl,vf610-i2c"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 reg = <0x0 0x2190000 0x0 0x10000>; 514 interrupts = <0 57 0x4>; 515 clock-names = "i2c"; 516 clocks = <&clockgen 4 0>; 517 status = "disabled"; 518 }; 519 520 i2c2: i2c@21a0000 { 521 compatible = "fsl,vf610-i2c"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0x0 0x21a0000 0x0 0x10000>; 525 interrupts = <0 58 0x4>; 526 clock-names = "i2c"; 527 clocks = <&clockgen 4 0>; 528 status = "disabled"; 529 }; 530 531 i2c3: i2c@21b0000 { 532 compatible = "fsl,vf610-i2c"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 reg = <0x0 0x21b0000 0x0 0x10000>; 536 interrupts = <0 59 0x4>; 537 clock-names = "i2c"; 538 clocks = <&clockgen 4 0>; 539 status = "disabled"; 540 }; 541 542 duart0: serial@21c0500 { 543 compatible = "fsl,ns16550", "ns16550a"; 544 reg = <0x00 0x21c0500 0x0 0x100>; 545 interrupts = <0 54 0x4>; 546 clocks = <&clockgen 4 0>; 547 }; 548 549 duart1: serial@21c0600 { 550 compatible = "fsl,ns16550", "ns16550a"; 551 reg = <0x00 0x21c0600 0x0 0x100>; 552 interrupts = <0 54 0x4>; 553 clocks = <&clockgen 4 0>; 554 }; 555 556 duart2: serial@21d0500 { 557 compatible = "fsl,ns16550", "ns16550a"; 558 reg = <0x0 0x21d0500 0x0 0x100>; 559 interrupts = <0 55 0x4>; 560 clocks = <&clockgen 4 0>; 561 }; 562 563 duart3: serial@21d0600 { 564 compatible = "fsl,ns16550", "ns16550a"; 565 reg = <0x0 0x21d0600 0x0 0x100>; 566 interrupts = <0 55 0x4>; 567 clocks = <&clockgen 4 0>; 568 }; 569 570 gpio1: gpio@2300000 { 571 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 572 reg = <0x0 0x2300000 0x0 0x10000>; 573 interrupts = <0 66 0x4>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 580 gpio2: gpio@2310000 { 581 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 582 reg = <0x0 0x2310000 0x0 0x10000>; 583 interrupts = <0 67 0x4>; 584 gpio-controller; 585 #gpio-cells = <2>; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 }; 589 590 gpio3: gpio@2320000 { 591 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 592 reg = <0x0 0x2320000 0x0 0x10000>; 593 interrupts = <0 68 0x4>; 594 gpio-controller; 595 #gpio-cells = <2>; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 600 gpio4: gpio@2330000 { 601 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 602 reg = <0x0 0x2330000 0x0 0x10000>; 603 interrupts = <0 134 0x4>; 604 gpio-controller; 605 #gpio-cells = <2>; 606 interrupt-controller; 607 #interrupt-cells = <2>; 608 }; 609 610 uqe: uqe@2400000 { 611 #address-cells = <1>; 612 #size-cells = <1>; 613 compatible = "fsl,qe", "simple-bus"; 614 ranges = <0x0 0x0 0x2400000 0x40000>; 615 reg = <0x0 0x2400000 0x0 0x480>; 616 brg-frequency = <100000000>; 617 bus-frequency = <200000000>; 618 fsl,qe-num-riscs = <1>; 619 fsl,qe-num-snums = <28>; 620 621 qeic: qeic@80 { 622 compatible = "fsl,qe-ic"; 623 reg = <0x80 0x80>; 624 #address-cells = <0>; 625 interrupt-controller; 626 #interrupt-cells = <1>; 627 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 629 }; 630 631 si1: si@700 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 compatible = "fsl,ls1043-qe-si", 635 "fsl,t1040-qe-si"; 636 reg = <0x700 0x80>; 637 }; 638 639 siram1: siram@1000 { 640 #address-cells = <1>; 641 #size-cells = <1>; 642 compatible = "fsl,ls1043-qe-siram", 643 "fsl,t1040-qe-siram"; 644 reg = <0x1000 0x800>; 645 }; 646 647 ucc@2000 { 648 cell-index = <1>; 649 reg = <0x2000 0x200>; 650 interrupts = <32>; 651 interrupt-parent = <&qeic>; 652 }; 653 654 ucc@2200 { 655 cell-index = <3>; 656 reg = <0x2200 0x200>; 657 interrupts = <34>; 658 interrupt-parent = <&qeic>; 659 }; 660 661 muram@10000 { 662 #address-cells = <1>; 663 #size-cells = <1>; 664 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 665 ranges = <0x0 0x10000 0x6000>; 666 667 data-only@0 { 668 compatible = "fsl,qe-muram-data", 669 "fsl,cpm-muram-data"; 670 reg = <0x0 0x6000>; 671 }; 672 }; 673 }; 674 675 lpuart0: serial@2950000 { 676 compatible = "fsl,ls1021a-lpuart"; 677 reg = <0x0 0x2950000 0x0 0x1000>; 678 interrupts = <0 48 0x4>; 679 clocks = <&clockgen 0 0>; 680 clock-names = "ipg"; 681 status = "disabled"; 682 }; 683 684 lpuart1: serial@2960000 { 685 compatible = "fsl,ls1021a-lpuart"; 686 reg = <0x0 0x2960000 0x0 0x1000>; 687 interrupts = <0 49 0x4>; 688 clocks = <&clockgen 4 0>; 689 clock-names = "ipg"; 690 status = "disabled"; 691 }; 692 693 lpuart2: serial@2970000 { 694 compatible = "fsl,ls1021a-lpuart"; 695 reg = <0x0 0x2970000 0x0 0x1000>; 696 interrupts = <0 50 0x4>; 697 clocks = <&clockgen 4 0>; 698 clock-names = "ipg"; 699 status = "disabled"; 700 }; 701 702 lpuart3: serial@2980000 { 703 compatible = "fsl,ls1021a-lpuart"; 704 reg = <0x0 0x2980000 0x0 0x1000>; 705 interrupts = <0 51 0x4>; 706 clocks = <&clockgen 4 0>; 707 clock-names = "ipg"; 708 status = "disabled"; 709 }; 710 711 lpuart4: serial@2990000 { 712 compatible = "fsl,ls1021a-lpuart"; 713 reg = <0x0 0x2990000 0x0 0x1000>; 714 interrupts = <0 52 0x4>; 715 clocks = <&clockgen 4 0>; 716 clock-names = "ipg"; 717 status = "disabled"; 718 }; 719 720 lpuart5: serial@29a0000 { 721 compatible = "fsl,ls1021a-lpuart"; 722 reg = <0x0 0x29a0000 0x0 0x1000>; 723 interrupts = <0 53 0x4>; 724 clocks = <&clockgen 4 0>; 725 clock-names = "ipg"; 726 status = "disabled"; 727 }; 728 729 wdog0: wdog@2ad0000 { 730 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 731 reg = <0x0 0x2ad0000 0x0 0x10000>; 732 interrupts = <0 83 0x4>; 733 clocks = <&clockgen 4 0>; 734 clock-names = "wdog"; 735 big-endian; 736 }; 737 738 edma0: edma@2c00000 { 739 #dma-cells = <2>; 740 compatible = "fsl,vf610-edma"; 741 reg = <0x0 0x2c00000 0x0 0x10000>, 742 <0x0 0x2c10000 0x0 0x10000>, 743 <0x0 0x2c20000 0x0 0x10000>; 744 interrupts = <0 103 0x4>, 745 <0 103 0x4>; 746 interrupt-names = "edma-tx", "edma-err"; 747 dma-channels = <32>; 748 big-endian; 749 clock-names = "dmamux0", "dmamux1"; 750 clocks = <&clockgen 4 0>, 751 <&clockgen 4 0>; 752 }; 753 754 usb0: usb3@2f00000 { 755 compatible = "snps,dwc3"; 756 reg = <0x0 0x2f00000 0x0 0x10000>; 757 interrupts = <0 60 0x4>; 758 dr_mode = "host"; 759 snps,quirk-frame-length-adjustment = <0x20>; 760 snps,dis_rxdet_inp3_quirk; 761 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 762 status = "disabled"; 763 }; 764 765 usb1: usb3@3000000 { 766 compatible = "snps,dwc3"; 767 reg = <0x0 0x3000000 0x0 0x10000>; 768 interrupts = <0 61 0x4>; 769 dr_mode = "host"; 770 snps,quirk-frame-length-adjustment = <0x20>; 771 snps,dis_rxdet_inp3_quirk; 772 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 773 status = "disabled"; 774 }; 775 776 usb2: usb3@3100000 { 777 compatible = "snps,dwc3"; 778 reg = <0x0 0x3100000 0x0 0x10000>; 779 interrupts = <0 63 0x4>; 780 dr_mode = "host"; 781 snps,quirk-frame-length-adjustment = <0x20>; 782 snps,dis_rxdet_inp3_quirk; 783 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 784 status = "disabled"; 785 }; 786 787 sata: sata@3200000 { 788 compatible = "fsl,ls1043a-ahci"; 789 reg = <0x0 0x3200000 0x0 0x10000>, 790 <0x0 0x20140520 0x0 0x4>; 791 reg-names = "ahci", "sata-ecc"; 792 interrupts = <0 69 0x4>; 793 clocks = <&clockgen 4 0>; 794 dma-coherent; 795 }; 796 797 msi1: msi-controller1@1571000 { 798 compatible = "fsl,ls1043a-msi"; 799 reg = <0x0 0x1571000 0x0 0x8>; 800 msi-controller; 801 interrupts = <0 116 0x4>; 802 }; 803 804 msi2: msi-controller2@1572000 { 805 compatible = "fsl,ls1043a-msi"; 806 reg = <0x0 0x1572000 0x0 0x8>; 807 msi-controller; 808 interrupts = <0 126 0x4>; 809 }; 810 811 msi3: msi-controller3@1573000 { 812 compatible = "fsl,ls1043a-msi"; 813 reg = <0x0 0x1573000 0x0 0x8>; 814 msi-controller; 815 interrupts = <0 160 0x4>; 816 }; 817 818 pcie1: pcie@3400000 { 819 compatible = "fsl,ls1043a-pcie"; 820 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 821 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 822 reg-names = "regs", "config"; 823 interrupts = <0 118 0x4>, /* controller interrupt */ 824 <0 117 0x4>; /* PME interrupt */ 825 interrupt-names = "intr", "pme"; 826 #address-cells = <3>; 827 #size-cells = <2>; 828 device_type = "pci"; 829 dma-coherent; 830 num-viewport = <6>; 831 bus-range = <0x0 0xff>; 832 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 833 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 834 msi-parent = <&msi1>, <&msi2>, <&msi3>; 835 #interrupt-cells = <1>; 836 interrupt-map-mask = <0 0 0 7>; 837 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, 838 <0000 0 0 2 &gic 0 111 0x4>, 839 <0000 0 0 3 &gic 0 112 0x4>, 840 <0000 0 0 4 &gic 0 113 0x4>; 841 status = "disabled"; 842 }; 843 844 pcie2: pcie@3500000 { 845 compatible = "fsl,ls1043a-pcie"; 846 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 847 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 848 reg-names = "regs", "config"; 849 interrupts = <0 128 0x4>, 850 <0 127 0x4>; 851 interrupt-names = "intr", "pme"; 852 #address-cells = <3>; 853 #size-cells = <2>; 854 device_type = "pci"; 855 dma-coherent; 856 num-viewport = <6>; 857 bus-range = <0x0 0xff>; 858 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 859 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 860 msi-parent = <&msi1>, <&msi2>, <&msi3>; 861 #interrupt-cells = <1>; 862 interrupt-map-mask = <0 0 0 7>; 863 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, 864 <0000 0 0 2 &gic 0 121 0x4>, 865 <0000 0 0 3 &gic 0 122 0x4>, 866 <0000 0 0 4 &gic 0 123 0x4>; 867 status = "disabled"; 868 }; 869 870 pcie3: pcie@3600000 { 871 compatible = "fsl,ls1043a-pcie"; 872 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 873 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 874 reg-names = "regs", "config"; 875 interrupts = <0 162 0x4>, 876 <0 161 0x4>; 877 interrupt-names = "intr", "pme"; 878 #address-cells = <3>; 879 #size-cells = <2>; 880 device_type = "pci"; 881 dma-coherent; 882 num-viewport = <6>; 883 bus-range = <0x0 0xff>; 884 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 885 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 886 msi-parent = <&msi1>, <&msi2>, <&msi3>; 887 #interrupt-cells = <1>; 888 interrupt-map-mask = <0 0 0 7>; 889 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, 890 <0000 0 0 2 &gic 0 155 0x4>, 891 <0000 0 0 3 &gic 0 156 0x4>, 892 <0000 0 0 4 &gic 0 157 0x4>; 893 status = "disabled"; 894 }; 895 896 qdma: dma-controller@8380000 { 897 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; 898 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 899 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 900 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 901 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 906 interrupt-names = "qdma-error", "qdma-queue0", 907 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 908 dma-channels = <8>; 909 block-number = <1>; 910 block-offset = <0x10000>; 911 fsl,dma-queues = <2>; 912 status-sizes = <64>; 913 queue-sizes = <64 64>; 914 big-endian; 915 }; 916 917 rcpm: power-controller@1ee2140 { 918 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; 919 reg = <0x0 0x1ee2140 0x0 0x4>; 920 #fsl,rcpm-wakeup-cells = <1>; 921 }; 922 923 ftm_alarm0: timer@29d0000 { 924 compatible = "fsl,ls1043a-ftm-alarm"; 925 reg = <0x0 0x29d0000 0x0 0x10000>; 926 fsl,rcpm-wakeup = <&rcpm 0x20000>; 927 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 928 big-endian; 929 }; 930 }; 931 932 firmware { 933 optee { 934 compatible = "linaro,optee-tz"; 935 method = "smc"; 936 }; 937 }; 938 939}; 940 941#include "qoriq-qman-portals.dtsi" 942#include "qoriq-bman-portals.dtsi" 943