1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_HW_H_ 5 #define _IGC_HW_H_ 6 7 #include <linux/types.h> 8 #include <linux/if_ether.h> 9 #include <linux/netdevice.h> 10 11 #include "igc_regs.h" 12 #include "igc_defines.h" 13 #include "igc_mac.h" 14 #include "igc_phy.h" 15 #include "igc_nvm.h" 16 #include "igc_i225.h" 17 #include "igc_base.h" 18 19 #define IGC_DEV_ID_I225_LM 0x15F2 20 #define IGC_DEV_ID_I225_V 0x15F3 21 #define IGC_DEV_ID_I225_I 0x15F8 22 #define IGC_DEV_ID_I220_V 0x15F7 23 #define IGC_DEV_ID_I225_K 0x3100 24 #define IGC_DEV_ID_I225_K2 0x3101 25 #define IGC_DEV_ID_I225_LMVP 0x5502 26 #define IGC_DEV_ID_I225_IT 0x0D9F 27 #define IGC_DEV_ID_I226_LM 0x125B 28 #define IGC_DEV_ID_I226_V 0x125C 29 #define IGC_DEV_ID_I226_IT 0x125D 30 #define IGC_DEV_ID_I221_V 0x125E 31 #define IGC_DEV_ID_I226_BLANK_NVM 0x125F 32 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 33 34 /* Function pointers for the MAC. */ 35 struct igc_mac_operations { 36 s32 (*check_for_link)(struct igc_hw *hw); 37 s32 (*reset_hw)(struct igc_hw *hw); 38 s32 (*init_hw)(struct igc_hw *hw); 39 s32 (*setup_physical_interface)(struct igc_hw *hw); 40 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 41 s32 (*read_mac_addr)(struct igc_hw *hw); 42 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 43 u16 *duplex); 44 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 45 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 46 }; 47 48 enum igc_mac_type { 49 igc_undefined = 0, 50 igc_i225, 51 igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 52 }; 53 54 enum igc_phy_type { 55 igc_phy_unknown = 0, 56 igc_phy_none, 57 igc_phy_i225, 58 }; 59 60 enum igc_media_type { 61 igc_media_type_unknown = 0, 62 igc_media_type_copper = 1, 63 igc_num_media_types 64 }; 65 66 enum igc_nvm_type { 67 igc_nvm_unknown = 0, 68 igc_nvm_eeprom_spi, 69 igc_nvm_flash_hw, 70 igc_nvm_invm, 71 }; 72 73 struct igc_info { 74 s32 (*get_invariants)(struct igc_hw *hw); 75 struct igc_mac_operations *mac_ops; 76 const struct igc_phy_operations *phy_ops; 77 struct igc_nvm_operations *nvm_ops; 78 }; 79 80 extern const struct igc_info igc_base_info; 81 82 struct igc_mac_info { 83 struct igc_mac_operations ops; 84 85 u8 addr[ETH_ALEN]; 86 u8 perm_addr[ETH_ALEN]; 87 88 enum igc_mac_type type; 89 90 u32 mc_filter_type; 91 92 u16 mta_reg_count; 93 u16 uta_reg_count; 94 95 u32 mta_shadow[MAX_MTA_REG]; 96 u16 rar_entry_count; 97 98 u8 forced_speed_duplex; 99 100 bool asf_firmware_present; 101 bool arc_subsystem_valid; 102 103 bool autoneg; 104 bool autoneg_failed; 105 bool get_link_status; 106 }; 107 108 struct igc_nvm_operations { 109 s32 (*acquire)(struct igc_hw *hw); 110 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 111 void (*release)(struct igc_hw *hw); 112 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 113 s32 (*update)(struct igc_hw *hw); 114 s32 (*validate)(struct igc_hw *hw); 115 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 116 }; 117 118 struct igc_phy_operations { 119 s32 (*acquire)(struct igc_hw *hw); 120 s32 (*check_reset_block)(struct igc_hw *hw); 121 s32 (*force_speed_duplex)(struct igc_hw *hw); 122 s32 (*get_phy_info)(struct igc_hw *hw); 123 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 124 void (*release)(struct igc_hw *hw); 125 s32 (*reset)(struct igc_hw *hw); 126 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 127 }; 128 129 struct igc_nvm_info { 130 struct igc_nvm_operations ops; 131 enum igc_nvm_type type; 132 133 u16 word_size; 134 u16 delay_usec; 135 u16 address_bits; 136 u16 opcode_bits; 137 u16 page_size; 138 }; 139 140 struct igc_phy_info { 141 struct igc_phy_operations ops; 142 143 enum igc_phy_type type; 144 145 u32 addr; 146 u32 id; 147 u32 reset_delay_us; /* in usec */ 148 u32 revision; 149 150 enum igc_media_type media_type; 151 152 u16 autoneg_advertised; 153 u16 autoneg_mask; 154 155 u8 mdix; 156 157 bool is_mdix; 158 bool speed_downgraded; 159 bool autoneg_wait_to_complete; 160 }; 161 162 struct igc_bus_info { 163 u16 func; 164 u16 pci_cmd_word; 165 }; 166 167 enum igc_fc_mode { 168 igc_fc_none = 0, 169 igc_fc_rx_pause, 170 igc_fc_tx_pause, 171 igc_fc_full, 172 igc_fc_default = 0xFF 173 }; 174 175 struct igc_fc_info { 176 u32 high_water; /* Flow control high-water mark */ 177 u32 low_water; /* Flow control low-water mark */ 178 u16 pause_time; /* Flow control pause timer */ 179 bool send_xon; /* Flow control send XON */ 180 bool strict_ieee; /* Strict IEEE mode */ 181 enum igc_fc_mode current_mode; /* Type of flow control */ 182 enum igc_fc_mode requested_mode; 183 }; 184 185 struct igc_dev_spec_base { 186 bool clear_semaphore_once; 187 bool eee_enable; 188 }; 189 190 struct igc_hw { 191 void *back; 192 193 u8 __iomem *hw_addr; 194 unsigned long io_base; 195 196 struct igc_mac_info mac; 197 struct igc_fc_info fc; 198 struct igc_nvm_info nvm; 199 struct igc_phy_info phy; 200 201 struct igc_bus_info bus; 202 203 union { 204 struct igc_dev_spec_base _base; 205 } dev_spec; 206 207 u16 device_id; 208 u16 subsystem_vendor_id; 209 u16 subsystem_device_id; 210 u16 vendor_id; 211 212 u8 revision_id; 213 }; 214 215 /* Statistics counters collected by the MAC */ 216 struct igc_hw_stats { 217 u64 crcerrs; 218 u64 algnerrc; 219 u64 symerrs; 220 u64 rxerrc; 221 u64 mpc; 222 u64 scc; 223 u64 ecol; 224 u64 mcc; 225 u64 latecol; 226 u64 colc; 227 u64 dc; 228 u64 tncrs; 229 u64 sec; 230 u64 cexterr; 231 u64 rlec; 232 u64 xonrxc; 233 u64 xontxc; 234 u64 xoffrxc; 235 u64 xofftxc; 236 u64 fcruc; 237 u64 prc64; 238 u64 prc127; 239 u64 prc255; 240 u64 prc511; 241 u64 prc1023; 242 u64 prc1522; 243 u64 tlpic; 244 u64 rlpic; 245 u64 gprc; 246 u64 bprc; 247 u64 mprc; 248 u64 gptc; 249 u64 gorc; 250 u64 gotc; 251 u64 rnbc; 252 u64 ruc; 253 u64 rfc; 254 u64 roc; 255 u64 rjc; 256 u64 mgprc; 257 u64 mgpdc; 258 u64 mgptc; 259 u64 tor; 260 u64 tot; 261 u64 tpr; 262 u64 tpt; 263 u64 ptc64; 264 u64 ptc127; 265 u64 ptc255; 266 u64 ptc511; 267 u64 ptc1023; 268 u64 ptc1522; 269 u64 mptc; 270 u64 bptc; 271 u64 tsctc; 272 u64 tsctfc; 273 u64 iac; 274 u64 htdpmc; 275 u64 rpthc; 276 u64 hgptc; 277 u64 hgorc; 278 u64 hgotc; 279 u64 lenerrs; 280 u64 scvpc; 281 u64 hrmpc; 282 u64 doosync; 283 u64 o2bgptc; 284 u64 o2bspc; 285 u64 b2ospc; 286 u64 b2ogprc; 287 }; 288 289 struct net_device *igc_get_hw_dev(struct igc_hw *hw); 290 #define hw_dbg(format, arg...) \ 291 netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 292 293 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 294 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 295 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 296 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 297 298 #endif /* _IGC_HW_H_ */ 299