1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 Cadence Design Systems Inc. 4 */ 5 6 #ifndef __PHY_MIPI_DPHY_H_ 7 #define __PHY_MIPI_DPHY_H_ 8 9 /** 10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set 11 * 12 * This structure is used to represent the configuration state of a 13 * MIPI D-PHY phy. 14 */ 15 struct phy_configure_opts_mipi_dphy { 16 /** 17 * @clk_miss: 18 * 19 * Timeout, in picoseconds, for receiver to detect absence of 20 * Clock transitions and disable the Clock Lane HS-RX. 21 * 22 * Maximum value: 60000 ps 23 */ 24 unsigned int clk_miss; 25 26 /** 27 * @clk_post: 28 * 29 * Time, in picoseconds, that the transmitter continues to 30 * send HS clock after the last associated Data Lane has 31 * transitioned to LP Mode. Interval is defined as the period 32 * from the end of @hs_trail to the beginning of @clk_trail. 33 * 34 * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps 35 */ 36 unsigned int clk_post; 37 38 /** 39 * @clk_pre: 40 * 41 * Time, in UI, that the HS clock shall be driven by 42 * the transmitter prior to any associated Data Lane beginning 43 * the transition from LP to HS mode. 44 * 45 * Minimum value: 8 UI 46 */ 47 unsigned int clk_pre; 48 49 /** 50 * @clk_prepare: 51 * 52 * Time, in picoseconds, that the transmitter drives the Clock 53 * Lane LP-00 Line state immediately before the HS-0 Line 54 * state starting the HS transmission. 55 * 56 * Minimum value: 38000 ps 57 * Maximum value: 95000 ps 58 */ 59 unsigned int clk_prepare; 60 61 /** 62 * @clk_settle: 63 * 64 * Time interval, in picoseconds, during which the HS receiver 65 * should ignore any Clock Lane HS transitions, starting from 66 * the beginning of @clk_prepare. 67 * 68 * Minimum value: 95000 ps 69 * Maximum value: 300000 ps 70 */ 71 unsigned int clk_settle; 72 73 /** 74 * @clk_term_en: 75 * 76 * Time, in picoseconds, for the Clock Lane receiver to enable 77 * the HS line termination. 78 * 79 * Maximum value: 38000 ps 80 */ 81 unsigned int clk_term_en; 82 83 /** 84 * @clk_trail: 85 * 86 * Time, in picoseconds, that the transmitter drives the HS-0 87 * state after the last payload clock bit of a HS transmission 88 * burst. 89 * 90 * Minimum value: 60000 ps 91 */ 92 unsigned int clk_trail; 93 94 /** 95 * @clk_zero: 96 * 97 * Time, in picoseconds, that the transmitter drives the HS-0 98 * state prior to starting the Clock. 99 */ 100 unsigned int clk_zero; 101 102 /** 103 * @d_term_en: 104 * 105 * Time, in picoseconds, for the Data Lane receiver to enable 106 * the HS line termination. 107 * 108 * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps 109 */ 110 unsigned int d_term_en; 111 112 /** 113 * @eot: 114 * 115 * Transmitted time interval, in picoseconds, from the start 116 * of @hs_trail or @clk_trail, to the start of the LP- 11 117 * state following a HS burst. 118 * 119 * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps 120 */ 121 unsigned int eot; 122 123 /** 124 * @hs_exit: 125 * 126 * Time, in picoseconds, that the transmitter drives LP-11 127 * following a HS burst. 128 * 129 * Minimum value: 100000 ps 130 */ 131 unsigned int hs_exit; 132 133 /** 134 * @hs_prepare: 135 * 136 * Time, in picoseconds, that the transmitter drives the Data 137 * Lane LP-00 Line state immediately before the HS-0 Line 138 * state starting the HS transmission. 139 * 140 * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps 141 * Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps 142 */ 143 unsigned int hs_prepare; 144 145 /** 146 * @hs_settle: 147 * 148 * Time interval, in picoseconds, during which the HS receiver 149 * shall ignore any Data Lane HS transitions, starting from 150 * the beginning of @hs_prepare. 151 * 152 * Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps 153 * Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps 154 */ 155 unsigned int hs_settle; 156 157 /** 158 * @hs_skip: 159 * 160 * Time interval, in picoseconds, during which the HS-RX 161 * should ignore any transitions on the Data Lane, following a 162 * HS burst. The end point of the interval is defined as the 163 * beginning of the LP-11 state following the HS burst. 164 * 165 * Minimum value: 40000 ps 166 * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps 167 */ 168 unsigned int hs_skip; 169 170 /** 171 * @hs_trail: 172 * 173 * Time, in picoseconds, that the transmitter drives the 174 * flipped differential state after last payload data bit of a 175 * HS transmission burst 176 * 177 * Minimum value: max(8 * @hs_clk_rate period in ps, 178 * 60000 ps + 4 * @hs_clk_rate period in ps) 179 */ 180 unsigned int hs_trail; 181 182 /** 183 * @hs_zero: 184 * 185 * Time, in picoseconds, that the transmitter drives the HS-0 186 * state prior to transmitting the Sync sequence. 187 */ 188 unsigned int hs_zero; 189 190 /** 191 * @init: 192 * 193 * Time, in microseconds for the initialization period to 194 * complete. 195 * 196 * Minimum value: 100 us 197 */ 198 unsigned int init; 199 200 /** 201 * @lpx: 202 * 203 * Transmitted length, in picoseconds, of any Low-Power state 204 * period. 205 * 206 * Minimum value: 50000 ps 207 */ 208 unsigned int lpx; 209 210 /** 211 * @ta_get: 212 * 213 * Time, in picoseconds, that the new transmitter drives the 214 * Bridge state (LP-00) after accepting control during a Link 215 * Turnaround. 216 * 217 * Value: 5 * @lpx 218 */ 219 unsigned int ta_get; 220 221 /** 222 * @ta_go: 223 * 224 * Time, in picoseconds, that the transmitter drives the 225 * Bridge state (LP-00) before releasing control during a Link 226 * Turnaround. 227 * 228 * Value: 4 * @lpx 229 */ 230 unsigned int ta_go; 231 232 /** 233 * @ta_sure: 234 * 235 * Time, in picoseconds, that the new transmitter waits after 236 * the LP-10 state before transmitting the Bridge state 237 * (LP-00) during a Link Turnaround. 238 * 239 * Minimum value: @lpx 240 * Maximum value: 2 * @lpx 241 */ 242 unsigned int ta_sure; 243 244 /** 245 * @wakeup: 246 * 247 * Time, in microseconds, that a transmitter drives a Mark-1 248 * state prior to a Stop state in order to initiate an exit 249 * from ULPS. 250 * 251 * Minimum value: 1000 us 252 */ 253 unsigned int wakeup; 254 255 /** 256 * @hs_clk_rate: 257 * 258 * Clock rate, in Hertz, of the high-speed clock. 259 */ 260 unsigned long hs_clk_rate; 261 262 /** 263 * @lp_clk_rate: 264 * 265 * Clock rate, in Hertz, of the low-power clock. 266 */ 267 unsigned long lp_clk_rate; 268 269 /** 270 * @lanes: 271 * 272 * Number of active, consecutive, data lanes, starting from 273 * lane 0, used for the transmissions. 274 */ 275 unsigned char lanes; 276 }; 277 278 int phy_mipi_dphy_get_default_config(unsigned long pixel_clock, 279 unsigned int bpp, 280 unsigned int lanes, 281 struct phy_configure_opts_mipi_dphy *cfg); 282 int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg); 283 284 #endif /* __PHY_MIPI_DPHY_H_ */ 285