1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
5 */
6
7 #ifndef __MT76x02_EEPROM_H
8 #define __MT76x02_EEPROM_H
9
10 #include "mt76x02.h"
11
12 enum mt76x02_eeprom_field {
13 MT_EE_CHIP_ID = 0x000,
14 MT_EE_VERSION = 0x002,
15 MT_EE_MAC_ADDR = 0x004,
16 MT_EE_PCI_ID = 0x00A,
17 MT_EE_ANTENNA = 0x022,
18 MT_EE_CFG1_INIT = 0x024,
19 MT_EE_NIC_CONF_0 = 0x034,
20 MT_EE_NIC_CONF_1 = 0x036,
21 MT_EE_COUNTRY_REGION_5GHZ = 0x038,
22 MT_EE_COUNTRY_REGION_2GHZ = 0x039,
23 MT_EE_FREQ_OFFSET = 0x03a,
24 MT_EE_NIC_CONF_2 = 0x042,
25
26 MT_EE_XTAL_TRIM_1 = 0x03a,
27 MT_EE_XTAL_TRIM_2 = 0x09e,
28
29 MT_EE_LNA_GAIN = 0x044,
30 MT_EE_RSSI_OFFSET_2G_0 = 0x046,
31 MT_EE_RSSI_OFFSET_2G_1 = 0x048,
32 MT_EE_LNA_GAIN_5GHZ_1 = 0x049,
33 MT_EE_RSSI_OFFSET_5G_0 = 0x04a,
34 MT_EE_RSSI_OFFSET_5G_1 = 0x04c,
35 MT_EE_LNA_GAIN_5GHZ_2 = 0x04d,
36
37 MT_EE_TX_POWER_DELTA_BW40 = 0x050,
38 MT_EE_TX_POWER_DELTA_BW80 = 0x052,
39
40 MT_EE_TX_POWER_EXT_PA_5G = 0x054,
41
42 MT_EE_TX_POWER_0_START_2G = 0x056,
43 MT_EE_TX_POWER_1_START_2G = 0x05c,
44
45 /* used as byte arrays */
46 #define MT_TX_POWER_GROUP_SIZE_5G 5
47 #define MT_TX_POWER_GROUPS_5G 6
48 MT_EE_TX_POWER_0_START_5G = 0x062,
49 MT_EE_TSSI_SLOPE_2G = 0x06e,
50
51 MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA = 0x074,
52 MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE = 0x076,
53
54 MT_EE_TX_POWER_1_START_5G = 0x080,
55
56 MT_EE_TX_POWER_CCK = 0x0a0,
57 MT_EE_TX_POWER_OFDM_2G_6M = 0x0a2,
58 MT_EE_TX_POWER_OFDM_2G_24M = 0x0a4,
59 MT_EE_TX_POWER_OFDM_5G_6M = 0x0b2,
60 MT_EE_TX_POWER_OFDM_5G_24M = 0x0b4,
61 MT_EE_TX_POWER_HT_MCS0 = 0x0a6,
62 MT_EE_TX_POWER_HT_MCS4 = 0x0a8,
63 MT_EE_TX_POWER_HT_MCS8 = 0x0aa,
64 MT_EE_TX_POWER_HT_MCS12 = 0x0ac,
65 MT_EE_TX_POWER_VHT_MCS0 = 0x0ba,
66 MT_EE_TX_POWER_VHT_MCS4 = 0x0bc,
67 MT_EE_TX_POWER_VHT_MCS8 = 0x0be,
68
69 MT_EE_2G_TARGET_POWER = 0x0d0,
70 MT_EE_TEMP_OFFSET = 0x0d1,
71 MT_EE_5G_TARGET_POWER = 0x0d2,
72 MT_EE_TSSI_BOUND1 = 0x0d4,
73 MT_EE_TSSI_BOUND2 = 0x0d6,
74 MT_EE_TSSI_BOUND3 = 0x0d8,
75 MT_EE_TSSI_BOUND4 = 0x0da,
76 MT_EE_FREQ_OFFSET_COMPENSATION = 0x0db,
77 MT_EE_TSSI_BOUND5 = 0x0dc,
78 MT_EE_TX_POWER_BYRATE_BASE = 0x0de,
79
80 MT_EE_TSSI_SLOPE_5G = 0x0f0,
81 MT_EE_RF_TEMP_COMP_SLOPE_5G = 0x0f2,
82 MT_EE_RF_TEMP_COMP_SLOPE_2G = 0x0f4,
83
84 MT_EE_RF_2G_TSSI_OFF_TXPOWER = 0x0f6,
85 MT_EE_RF_2G_RX_HIGH_GAIN = 0x0f8,
86 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN = 0x0fa,
87 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN = 0x0fc,
88 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN = 0x0fe,
89
90 MT_EE_BT_RCAL_RESULT = 0x138,
91 MT_EE_BT_VCDL_CALIBRATION = 0x13c,
92 MT_EE_BT_PMUCFG = 0x13e,
93
94 MT_EE_USAGE_MAP_START = 0x1e0,
95 MT_EE_USAGE_MAP_END = 0x1fc,
96
97 __MT_EE_MAX
98 };
99
100 #define MT_EE_ANTENNA_DUAL BIT(15)
101
102 #define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)
103 #define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)
104 #define MT_EE_NIC_CONF_0_PA_TYPE GENMASK(9, 8)
105 #define MT_EE_NIC_CONF_0_PA_INT_2G BIT(8)
106 #define MT_EE_NIC_CONF_0_PA_INT_5G BIT(9)
107 #define MT_EE_NIC_CONF_0_PA_IO_CURRENT BIT(10)
108 #define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)
109
110 #define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0)
111 #define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1)
112 #define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2)
113 #define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3)
114 #define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13)
115
116 #define MT_EE_NIC_CONF_2_ANT_OPT BIT(3)
117 #define MT_EE_NIC_CONF_2_ANT_DIV BIT(4)
118 #define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)
119
120 #define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \
121 MT_EE_USAGE_MAP_START + 1)
122
123 enum mt76x02_eeprom_modes {
124 MT_EE_READ,
125 MT_EE_PHYSICAL_READ,
126 };
127
128 enum mt76x02_board_type {
129 BOARD_TYPE_2GHZ = 1,
130 BOARD_TYPE_5GHZ = 2,
131 };
132
mt76x02_field_valid(u8 val)133 static inline bool mt76x02_field_valid(u8 val)
134 {
135 return val != 0 && val != 0xff;
136 }
137
138 static inline int
mt76x02_sign_extend(u32 val,unsigned int size)139 mt76x02_sign_extend(u32 val, unsigned int size)
140 {
141 bool sign = val & BIT(size - 1);
142
143 val &= BIT(size - 1) - 1;
144
145 return sign ? val : -val;
146 }
147
148 static inline int
mt76x02_sign_extend_optional(u32 val,unsigned int size)149 mt76x02_sign_extend_optional(u32 val, unsigned int size)
150 {
151 bool enable = val & BIT(size);
152
153 return enable ? mt76x02_sign_extend(val, size) : 0;
154 }
155
mt76x02_rate_power_val(u8 val)156 static inline s8 mt76x02_rate_power_val(u8 val)
157 {
158 if (!mt76x02_field_valid(val))
159 return 0;
160
161 return mt76x02_sign_extend_optional(val, 7);
162 }
163
164 static inline int
mt76x02_eeprom_get(struct mt76x02_dev * dev,enum mt76x02_eeprom_field field)165 mt76x02_eeprom_get(struct mt76x02_dev *dev,
166 enum mt76x02_eeprom_field field)
167 {
168 if ((field & 1) || field >= __MT_EE_MAX)
169 return -1;
170
171 return get_unaligned_le16(dev->mt76.eeprom.data + field);
172 }
173
174 bool mt76x02_ext_pa_enabled(struct mt76x02_dev *dev, enum nl80211_band band);
175 int mt76x02_get_efuse_data(struct mt76x02_dev *dev, u16 base, void *buf,
176 int len, enum mt76x02_eeprom_modes mode);
177 void mt76x02_get_rx_gain(struct mt76x02_dev *dev, enum nl80211_band band,
178 u16 *rssi_offset, s8 *lna_2g, s8 *lna_5g);
179 u8 mt76x02_get_lna_gain(struct mt76x02_dev *dev,
180 s8 *lna_2g, s8 *lna_5g,
181 struct ieee80211_channel *chan);
182 void mt76x02_eeprom_parse_hw_cap(struct mt76x02_dev *dev);
183 int mt76x02_eeprom_copy(struct mt76x02_dev *dev,
184 enum mt76x02_eeprom_field field,
185 void *dest, int len);
186
187 #endif /* __MT76x02_EEPROM_H */
188