1 /************************************************************************** 2 * 3 * Copyright 2008 VMware, Inc. 4 * Copyright 2009-2010 VMware, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 **************************************************************************/ 28 29 #ifndef P_SHADER_TOKENS_H 30 #define P_SHADER_TOKENS_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 37 struct tgsi_header 38 { 39 unsigned HeaderSize : 8; 40 unsigned BodySize : 24; 41 }; 42 43 struct tgsi_processor 44 { 45 unsigned Processor : 4; /* PIPE_SHADER_ */ 46 unsigned Padding : 28; 47 }; 48 49 enum tgsi_token_type { 50 TGSI_TOKEN_TYPE_DECLARATION, 51 TGSI_TOKEN_TYPE_IMMEDIATE, 52 TGSI_TOKEN_TYPE_INSTRUCTION, 53 TGSI_TOKEN_TYPE_PROPERTY, 54 }; 55 56 struct tgsi_token 57 { 58 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_x */ 59 unsigned NrTokens : 8; /**< UINT */ 60 unsigned Padding : 20; 61 }; 62 63 enum tgsi_file_type { 64 TGSI_FILE_NULL, 65 TGSI_FILE_CONSTANT, 66 TGSI_FILE_INPUT, 67 TGSI_FILE_OUTPUT, 68 TGSI_FILE_TEMPORARY, 69 TGSI_FILE_SAMPLER, 70 TGSI_FILE_ADDRESS, 71 TGSI_FILE_IMMEDIATE, 72 TGSI_FILE_SYSTEM_VALUE, 73 TGSI_FILE_IMAGE, 74 TGSI_FILE_SAMPLER_VIEW, 75 TGSI_FILE_BUFFER, 76 TGSI_FILE_MEMORY, 77 TGSI_FILE_CONSTBUF, 78 TGSI_FILE_HW_ATOMIC, 79 TGSI_FILE_COUNT, /**< how many TGSI_FILE_ types */ 80 }; 81 82 83 #define TGSI_WRITEMASK_NONE 0x00 84 #define TGSI_WRITEMASK_X 0x01 85 #define TGSI_WRITEMASK_Y 0x02 86 #define TGSI_WRITEMASK_XY 0x03 87 #define TGSI_WRITEMASK_Z 0x04 88 #define TGSI_WRITEMASK_XZ 0x05 89 #define TGSI_WRITEMASK_YZ 0x06 90 #define TGSI_WRITEMASK_XYZ 0x07 91 #define TGSI_WRITEMASK_W 0x08 92 #define TGSI_WRITEMASK_XW 0x09 93 #define TGSI_WRITEMASK_YW 0x0A 94 #define TGSI_WRITEMASK_XYW 0x0B 95 #define TGSI_WRITEMASK_ZW 0x0C 96 #define TGSI_WRITEMASK_XZW 0x0D 97 #define TGSI_WRITEMASK_YZW 0x0E 98 #define TGSI_WRITEMASK_XYZW 0x0F 99 100 enum tgsi_interpolate_mode { 101 TGSI_INTERPOLATE_CONSTANT, 102 TGSI_INTERPOLATE_LINEAR, 103 TGSI_INTERPOLATE_PERSPECTIVE, 104 TGSI_INTERPOLATE_COLOR, /* special color case for smooth/flat */ 105 TGSI_INTERPOLATE_COUNT, 106 }; 107 108 enum tgsi_interpolate_loc { 109 TGSI_INTERPOLATE_LOC_CENTER, 110 TGSI_INTERPOLATE_LOC_CENTROID, 111 TGSI_INTERPOLATE_LOC_SAMPLE, 112 TGSI_INTERPOLATE_LOC_COUNT, 113 }; 114 115 enum tgsi_memory_type { 116 TGSI_MEMORY_TYPE_GLOBAL, /* OpenCL global */ 117 TGSI_MEMORY_TYPE_SHARED, /* OpenCL local / GLSL shared */ 118 TGSI_MEMORY_TYPE_PRIVATE, /* OpenCL private */ 119 TGSI_MEMORY_TYPE_INPUT, /* OpenCL kernel input params */ 120 TGSI_MEMORY_TYPE_COUNT, 121 }; 122 123 struct tgsi_declaration 124 { 125 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_DECLARATION */ 126 unsigned NrTokens : 8; /**< UINT */ 127 unsigned File : 4; /**< one of TGSI_FILE_x */ 128 unsigned UsageMask : 4; /**< bitmask of TGSI_WRITEMASK_x flags */ 129 unsigned Dimension : 1; /**< any extra dimension info? */ 130 unsigned Semantic : 1; /**< BOOL, any semantic info? */ 131 unsigned Interpolate : 1; /**< any interpolation info? */ 132 unsigned Invariant : 1; /**< invariant optimization? */ 133 unsigned Local : 1; /**< optimize as subroutine local variable? */ 134 unsigned Array : 1; /**< extra array info? */ 135 unsigned Atomic : 1; /**< atomic only? for TGSI_FILE_BUFFER */ 136 unsigned MemType : 2; /**< TGSI_MEMORY_TYPE_x for TGSI_FILE_MEMORY */ 137 unsigned Padding : 3; 138 }; 139 140 struct tgsi_declaration_range 141 { 142 unsigned First : 16; /**< UINT */ 143 unsigned Last : 16; /**< UINT */ 144 }; 145 146 struct tgsi_declaration_dimension 147 { 148 unsigned Index2D:16; /**< UINT */ 149 unsigned Padding:16; 150 }; 151 152 struct tgsi_declaration_interp 153 { 154 unsigned Interpolate : 4; /**< one of TGSI_INTERPOLATE_x */ 155 unsigned Location : 2; /**< one of TGSI_INTERPOLATE_LOC_x */ 156 unsigned Padding : 26; 157 }; 158 159 enum tgsi_semantic { 160 TGSI_SEMANTIC_POSITION, 161 TGSI_SEMANTIC_COLOR, 162 TGSI_SEMANTIC_BCOLOR, /**< back-face color */ 163 TGSI_SEMANTIC_FOG, 164 TGSI_SEMANTIC_PSIZE, 165 TGSI_SEMANTIC_GENERIC, 166 TGSI_SEMANTIC_NORMAL, 167 TGSI_SEMANTIC_FACE, 168 TGSI_SEMANTIC_EDGEFLAG, 169 TGSI_SEMANTIC_PRIMID, 170 TGSI_SEMANTIC_INSTANCEID, /**< doesn't include start_instance */ 171 TGSI_SEMANTIC_VERTEXID, 172 TGSI_SEMANTIC_STENCIL, 173 TGSI_SEMANTIC_CLIPDIST, 174 TGSI_SEMANTIC_CLIPVERTEX, 175 TGSI_SEMANTIC_GRID_SIZE, /**< grid size in blocks */ 176 TGSI_SEMANTIC_BLOCK_ID, /**< id of the current block */ 177 TGSI_SEMANTIC_BLOCK_SIZE, /**< block size in threads */ 178 TGSI_SEMANTIC_THREAD_ID, /**< block-relative id of the current thread */ 179 TGSI_SEMANTIC_TEXCOORD, /**< texture or sprite coordinates */ 180 TGSI_SEMANTIC_PCOORD, /**< point sprite coordinate */ 181 TGSI_SEMANTIC_VIEWPORT_INDEX, /**< viewport index */ 182 TGSI_SEMANTIC_LAYER, /**< layer (rendertarget index) */ 183 TGSI_SEMANTIC_SAMPLEID, 184 TGSI_SEMANTIC_SAMPLEPOS, 185 TGSI_SEMANTIC_SAMPLEMASK, 186 TGSI_SEMANTIC_INVOCATIONID, 187 TGSI_SEMANTIC_VERTEXID_NOBASE, 188 TGSI_SEMANTIC_BASEVERTEX, 189 TGSI_SEMANTIC_PATCH, /**< generic per-patch semantic */ 190 TGSI_SEMANTIC_TESSCOORD, /**< coordinate being processed by tess */ 191 TGSI_SEMANTIC_TESSOUTER, /**< outer tessellation levels */ 192 TGSI_SEMANTIC_TESSINNER, /**< inner tessellation levels */ 193 TGSI_SEMANTIC_VERTICESIN, /**< number of input vertices */ 194 TGSI_SEMANTIC_HELPER_INVOCATION, /**< current invocation is helper */ 195 TGSI_SEMANTIC_BASEINSTANCE, 196 TGSI_SEMANTIC_DRAWID, 197 TGSI_SEMANTIC_WORK_DIM, /**< opencl get_work_dim value */ 198 TGSI_SEMANTIC_SUBGROUP_SIZE, 199 TGSI_SEMANTIC_SUBGROUP_INVOCATION, 200 TGSI_SEMANTIC_SUBGROUP_EQ_MASK, 201 TGSI_SEMANTIC_SUBGROUP_GE_MASK, 202 TGSI_SEMANTIC_SUBGROUP_GT_MASK, 203 TGSI_SEMANTIC_SUBGROUP_LE_MASK, 204 TGSI_SEMANTIC_SUBGROUP_LT_MASK, 205 TGSI_SEMANTIC_CS_USER_DATA_AMD, 206 TGSI_SEMANTIC_VIEWPORT_MASK, 207 TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL, /**< from set_tess_state */ 208 TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL, /**< from set_tess_state */ 209 TGSI_SEMANTIC_COUNT, /**< number of semantic values */ 210 }; 211 212 struct tgsi_declaration_semantic 213 { 214 unsigned Name : 8; /**< one of TGSI_SEMANTIC_x */ 215 unsigned Index : 16; /**< UINT */ 216 unsigned StreamX : 2; /**< vertex stream (for GS output) */ 217 unsigned StreamY : 2; 218 unsigned StreamZ : 2; 219 unsigned StreamW : 2; 220 }; 221 222 struct tgsi_declaration_image { 223 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */ 224 unsigned Raw : 1; 225 unsigned Writable : 1; 226 unsigned Format : 10; /**< one of PIPE_FORMAT_ */ 227 unsigned Padding : 12; 228 }; 229 230 enum tgsi_return_type { 231 TGSI_RETURN_TYPE_UNORM = 0, 232 TGSI_RETURN_TYPE_SNORM, 233 TGSI_RETURN_TYPE_SINT, 234 TGSI_RETURN_TYPE_UINT, 235 TGSI_RETURN_TYPE_FLOAT, 236 TGSI_RETURN_TYPE_UNKNOWN, 237 TGSI_RETURN_TYPE_COUNT 238 }; 239 240 struct tgsi_declaration_sampler_view { 241 unsigned Resource : 8; /**< one of TGSI_TEXTURE_ */ 242 unsigned ReturnTypeX : 6; /**< one of enum tgsi_return_type */ 243 unsigned ReturnTypeY : 6; /**< one of enum tgsi_return_type */ 244 unsigned ReturnTypeZ : 6; /**< one of enum tgsi_return_type */ 245 unsigned ReturnTypeW : 6; /**< one of enum tgsi_return_type */ 246 }; 247 248 struct tgsi_declaration_array { 249 unsigned ArrayID : 10; 250 unsigned Padding : 22; 251 }; 252 253 enum tgsi_imm_type { 254 TGSI_IMM_FLOAT32, 255 TGSI_IMM_UINT32, 256 TGSI_IMM_INT32, 257 TGSI_IMM_FLOAT64, 258 TGSI_IMM_UINT64, 259 TGSI_IMM_INT64, 260 }; 261 262 struct tgsi_immediate 263 { 264 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_IMMEDIATE */ 265 unsigned NrTokens : 14; /**< UINT */ 266 unsigned DataType : 4; /**< one of TGSI_IMM_x */ 267 unsigned Padding : 10; 268 }; 269 270 union tgsi_immediate_data 271 { 272 float Float; 273 unsigned Uint; 274 int Int; 275 }; 276 277 enum tgsi_property_name { 278 TGSI_PROPERTY_GS_INPUT_PRIM, 279 TGSI_PROPERTY_GS_OUTPUT_PRIM, 280 TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES, 281 TGSI_PROPERTY_FS_COORD_ORIGIN, 282 TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, 283 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS, 284 TGSI_PROPERTY_FS_DEPTH_LAYOUT, 285 TGSI_PROPERTY_VS_PROHIBIT_UCPS, 286 TGSI_PROPERTY_GS_INVOCATIONS, 287 TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, 288 TGSI_PROPERTY_TCS_VERTICES_OUT, 289 TGSI_PROPERTY_TES_PRIM_MODE, 290 TGSI_PROPERTY_TES_SPACING, 291 TGSI_PROPERTY_TES_VERTEX_ORDER_CW, 292 TGSI_PROPERTY_TES_POINT_MODE, 293 TGSI_PROPERTY_NUM_CLIPDIST_ENABLED, 294 TGSI_PROPERTY_NUM_CULLDIST_ENABLED, 295 TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL, 296 TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE, 297 TGSI_PROPERTY_NEXT_SHADER, 298 TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 299 TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 300 TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 301 TGSI_PROPERTY_MUL_ZERO_WINS, 302 TGSI_PROPERTY_VS_BLIT_SGPRS_AMD, 303 TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD, 304 TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE, 305 TGSI_PROPERTY_FS_BLEND_EQUATION_ADVANCED, 306 TGSI_PROPERTY_COUNT, 307 }; 308 309 struct tgsi_property { 310 unsigned Type : 4; /**< TGSI_TOKEN_TYPE_PROPERTY */ 311 unsigned NrTokens : 8; /**< UINT */ 312 unsigned PropertyName : 8; /**< one of TGSI_PROPERTY */ 313 unsigned Padding : 12; 314 }; 315 316 enum tgsi_fs_coord_origin { 317 TGSI_FS_COORD_ORIGIN_UPPER_LEFT, 318 TGSI_FS_COORD_ORIGIN_LOWER_LEFT, 319 }; 320 321 enum tgsi_fs_coord_pixcenter { 322 TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER, 323 TGSI_FS_COORD_PIXEL_CENTER_INTEGER, 324 }; 325 326 enum tgsi_fs_depth_layout { 327 TGSI_FS_DEPTH_LAYOUT_NONE, 328 TGSI_FS_DEPTH_LAYOUT_ANY, 329 TGSI_FS_DEPTH_LAYOUT_GREATER, 330 TGSI_FS_DEPTH_LAYOUT_LESS, 331 TGSI_FS_DEPTH_LAYOUT_UNCHANGED, 332 }; 333 334 struct tgsi_property_data { 335 unsigned Data; 336 }; 337 338 /* TGSI opcodes. 339 * 340 * For more information on semantics of opcodes and 341 * which APIs are known to use which opcodes, see 342 * gallium/docs/source/tgsi.rst 343 */ 344 enum tgsi_opcode { 345 TGSI_OPCODE_ARL = 0, 346 TGSI_OPCODE_MOV = 1, 347 TGSI_OPCODE_LIT = 2, 348 TGSI_OPCODE_RCP = 3, 349 TGSI_OPCODE_RSQ = 4, 350 TGSI_OPCODE_EXP = 5, 351 TGSI_OPCODE_LOG = 6, 352 TGSI_OPCODE_MUL = 7, 353 TGSI_OPCODE_ADD = 8, 354 TGSI_OPCODE_DP3 = 9, 355 TGSI_OPCODE_DP4 = 10, 356 TGSI_OPCODE_DST = 11, 357 TGSI_OPCODE_MIN = 12, 358 TGSI_OPCODE_MAX = 13, 359 TGSI_OPCODE_SLT = 14, 360 TGSI_OPCODE_SGE = 15, 361 TGSI_OPCODE_MAD = 16, 362 TGSI_OPCODE_TEX_LZ = 17, 363 TGSI_OPCODE_LRP = 18, 364 TGSI_OPCODE_FMA = 19, 365 TGSI_OPCODE_SQRT = 20, 366 TGSI_OPCODE_LDEXP = 21, 367 TGSI_OPCODE_F2U64 = 22, 368 TGSI_OPCODE_F2I64 = 23, 369 TGSI_OPCODE_FRC = 24, 370 TGSI_OPCODE_TXF_LZ = 25, 371 TGSI_OPCODE_FLR = 26, 372 TGSI_OPCODE_ROUND = 27, 373 TGSI_OPCODE_EX2 = 28, 374 TGSI_OPCODE_LG2 = 29, 375 TGSI_OPCODE_POW = 30, 376 TGSI_OPCODE_DEMOTE = 31, 377 TGSI_OPCODE_U2I64 = 32, 378 TGSI_OPCODE_CLOCK = 33, 379 TGSI_OPCODE_I2I64 = 34, 380 TGSI_OPCODE_READ_HELPER = 35, 381 TGSI_OPCODE_COS = 36, 382 TGSI_OPCODE_DDX = 37, 383 TGSI_OPCODE_DDY = 38, 384 TGSI_OPCODE_KILL = 39 /* unconditional */, 385 TGSI_OPCODE_PK2H = 40, 386 TGSI_OPCODE_PK2US = 41, 387 TGSI_OPCODE_PK4B = 42, 388 TGSI_OPCODE_PK4UB = 43, 389 TGSI_OPCODE_D2U64 = 44, 390 TGSI_OPCODE_SEQ = 45, 391 TGSI_OPCODE_D2I64 = 46, 392 TGSI_OPCODE_SGT = 47, 393 TGSI_OPCODE_SIN = 48, 394 TGSI_OPCODE_SLE = 49, 395 TGSI_OPCODE_SNE = 50, 396 TGSI_OPCODE_U642D = 51, 397 TGSI_OPCODE_TEX = 52, 398 TGSI_OPCODE_TXD = 53, 399 TGSI_OPCODE_TXP = 54, 400 TGSI_OPCODE_UP2H = 55, 401 TGSI_OPCODE_UP2US = 56, 402 TGSI_OPCODE_UP4B = 57, 403 TGSI_OPCODE_UP4UB = 58, 404 TGSI_OPCODE_U642F = 59, 405 TGSI_OPCODE_I642F = 60, 406 TGSI_OPCODE_ARR = 61, 407 TGSI_OPCODE_I642D = 62, 408 TGSI_OPCODE_CAL = 63, 409 TGSI_OPCODE_RET = 64, 410 TGSI_OPCODE_SSG = 65 /* SGN */, 411 TGSI_OPCODE_CMP = 66, 412 /* gap */ 413 TGSI_OPCODE_TXB = 68, 414 TGSI_OPCODE_FBFETCH = 69, 415 TGSI_OPCODE_DIV = 70, 416 TGSI_OPCODE_DP2 = 71, 417 TGSI_OPCODE_TXL = 72, 418 TGSI_OPCODE_BRK = 73, 419 TGSI_OPCODE_IF = 74, 420 TGSI_OPCODE_UIF = 75, 421 TGSI_OPCODE_READ_INVOC = 76, 422 TGSI_OPCODE_ELSE = 77, 423 TGSI_OPCODE_ENDIF = 78, 424 TGSI_OPCODE_DDX_FINE = 79, 425 TGSI_OPCODE_DDY_FINE = 80, 426 /* gap */ 427 TGSI_OPCODE_CEIL = 83, 428 TGSI_OPCODE_I2F = 84, 429 TGSI_OPCODE_NOT = 85, 430 TGSI_OPCODE_TRUNC = 86, 431 TGSI_OPCODE_SHL = 87, 432 TGSI_OPCODE_BALLOT = 88, 433 TGSI_OPCODE_AND = 89, 434 TGSI_OPCODE_OR = 90, 435 TGSI_OPCODE_MOD = 91, 436 TGSI_OPCODE_XOR = 92, 437 /* gap */ 438 TGSI_OPCODE_TXF = 94, 439 TGSI_OPCODE_TXQ = 95, 440 TGSI_OPCODE_CONT = 96, 441 TGSI_OPCODE_EMIT = 97, 442 TGSI_OPCODE_ENDPRIM = 98, 443 TGSI_OPCODE_BGNLOOP = 99, 444 TGSI_OPCODE_BGNSUB = 100, 445 TGSI_OPCODE_ENDLOOP = 101, 446 TGSI_OPCODE_ENDSUB = 102, 447 TGSI_OPCODE_ATOMFADD = 103, 448 TGSI_OPCODE_TXQS = 104, 449 TGSI_OPCODE_RESQ = 105, 450 TGSI_OPCODE_READ_FIRST = 106, 451 TGSI_OPCODE_NOP = 107, 452 453 TGSI_OPCODE_FSEQ = 108, 454 TGSI_OPCODE_FSGE = 109, 455 TGSI_OPCODE_FSLT = 110, 456 TGSI_OPCODE_FSNE = 111, 457 458 TGSI_OPCODE_MEMBAR = 112, 459 /* gap */ 460 TGSI_OPCODE_KILL_IF = 116 /* conditional kill */, 461 TGSI_OPCODE_END = 117 /* aka HALT */, 462 TGSI_OPCODE_DFMA = 118, 463 TGSI_OPCODE_F2I = 119, 464 TGSI_OPCODE_IDIV = 120, 465 TGSI_OPCODE_IMAX = 121, 466 TGSI_OPCODE_IMIN = 122, 467 TGSI_OPCODE_INEG = 123, 468 TGSI_OPCODE_ISGE = 124, 469 TGSI_OPCODE_ISHR = 125, 470 TGSI_OPCODE_ISLT = 126, 471 TGSI_OPCODE_F2U = 127, 472 TGSI_OPCODE_U2F = 128, 473 TGSI_OPCODE_UADD = 129, 474 TGSI_OPCODE_UDIV = 130, 475 TGSI_OPCODE_UMAD = 131, 476 TGSI_OPCODE_UMAX = 132, 477 TGSI_OPCODE_UMIN = 133, 478 TGSI_OPCODE_UMOD = 134, 479 TGSI_OPCODE_UMUL = 135, 480 TGSI_OPCODE_USEQ = 136, 481 TGSI_OPCODE_USGE = 137, 482 TGSI_OPCODE_USHR = 138, 483 TGSI_OPCODE_USLT = 139, 484 TGSI_OPCODE_USNE = 140, 485 TGSI_OPCODE_SWITCH = 141, 486 TGSI_OPCODE_CASE = 142, 487 TGSI_OPCODE_DEFAULT = 143, 488 TGSI_OPCODE_ENDSWITCH = 144, 489 490 /* resource related opcodes */ 491 TGSI_OPCODE_SAMPLE = 145, 492 TGSI_OPCODE_SAMPLE_I = 146, 493 TGSI_OPCODE_SAMPLE_I_MS = 147, 494 TGSI_OPCODE_SAMPLE_B = 148, 495 TGSI_OPCODE_SAMPLE_C = 149, 496 TGSI_OPCODE_SAMPLE_C_LZ = 150, 497 TGSI_OPCODE_SAMPLE_D = 151, 498 TGSI_OPCODE_SAMPLE_L = 152, 499 TGSI_OPCODE_GATHER4 = 153, 500 TGSI_OPCODE_SVIEWINFO = 154, 501 TGSI_OPCODE_SAMPLE_POS = 155, 502 TGSI_OPCODE_SAMPLE_INFO = 156, 503 504 TGSI_OPCODE_UARL = 157, 505 TGSI_OPCODE_UCMP = 158, 506 TGSI_OPCODE_IABS = 159, 507 TGSI_OPCODE_ISSG = 160, 508 509 TGSI_OPCODE_LOAD = 161, 510 TGSI_OPCODE_STORE = 162, 511 TGSI_OPCODE_IMG2HND = 163, 512 TGSI_OPCODE_SAMP2HND = 164, 513 /* gap */ 514 TGSI_OPCODE_BARRIER = 166, 515 516 TGSI_OPCODE_ATOMUADD = 167, 517 TGSI_OPCODE_ATOMXCHG = 168, 518 TGSI_OPCODE_ATOMCAS = 169, 519 TGSI_OPCODE_ATOMAND = 170, 520 TGSI_OPCODE_ATOMOR = 171, 521 TGSI_OPCODE_ATOMXOR = 172, 522 TGSI_OPCODE_ATOMUMIN = 173, 523 TGSI_OPCODE_ATOMUMAX = 174, 524 TGSI_OPCODE_ATOMIMIN = 175, 525 TGSI_OPCODE_ATOMIMAX = 176, 526 527 /* to be used for shadow cube map compares */ 528 TGSI_OPCODE_TEX2 = 177, 529 TGSI_OPCODE_TXB2 = 178, 530 TGSI_OPCODE_TXL2 = 179, 531 532 TGSI_OPCODE_IMUL_HI = 180, 533 TGSI_OPCODE_UMUL_HI = 181, 534 535 TGSI_OPCODE_TG4 = 182, 536 537 TGSI_OPCODE_LODQ = 183, 538 539 TGSI_OPCODE_IBFE = 184, 540 TGSI_OPCODE_UBFE = 185, 541 TGSI_OPCODE_BFI = 186, 542 TGSI_OPCODE_BREV = 187, 543 TGSI_OPCODE_POPC = 188, 544 TGSI_OPCODE_LSB = 189, 545 TGSI_OPCODE_IMSB = 190, 546 TGSI_OPCODE_UMSB = 191, 547 548 TGSI_OPCODE_INTERP_CENTROID = 192, 549 TGSI_OPCODE_INTERP_SAMPLE = 193, 550 TGSI_OPCODE_INTERP_OFFSET = 194, 551 552 /* sm5 marked opcodes are supported in D3D11 optionally - also DMOV, DMOVC */ 553 TGSI_OPCODE_F2D = 195 /* SM5 */, 554 TGSI_OPCODE_D2F = 196, 555 TGSI_OPCODE_DABS = 197, 556 TGSI_OPCODE_DNEG = 198 /* SM5 */, 557 TGSI_OPCODE_DADD = 199 /* SM5 */, 558 TGSI_OPCODE_DMUL = 200 /* SM5 */, 559 TGSI_OPCODE_DMAX = 201 /* SM5 */, 560 TGSI_OPCODE_DMIN = 202 /* SM5 */, 561 TGSI_OPCODE_DSLT = 203 /* SM5 */, 562 TGSI_OPCODE_DSGE = 204 /* SM5 */, 563 TGSI_OPCODE_DSEQ = 205 /* SM5 */, 564 TGSI_OPCODE_DSNE = 206 /* SM5 */, 565 TGSI_OPCODE_DRCP = 207 /* eg, cayman */, 566 TGSI_OPCODE_DSQRT = 208 /* eg, cayman also has DRSQ */, 567 TGSI_OPCODE_DMAD = 209, 568 TGSI_OPCODE_DFRAC = 210 /* eg, cayman */, 569 TGSI_OPCODE_DLDEXP = 211 /* eg, cayman */, 570 TGSI_OPCODE_DFRACEXP = 212 /* eg, cayman */, 571 TGSI_OPCODE_D2I = 213, 572 TGSI_OPCODE_I2D = 214, 573 TGSI_OPCODE_D2U = 215, 574 TGSI_OPCODE_U2D = 216, 575 TGSI_OPCODE_DRSQ = 217 /* eg, cayman also has DRSQ */, 576 TGSI_OPCODE_DTRUNC = 218 /* nvc0 */, 577 TGSI_OPCODE_DCEIL = 219 /* nvc0 */, 578 TGSI_OPCODE_DFLR = 220 /* nvc0 */, 579 TGSI_OPCODE_DROUND = 221 /* nvc0 */, 580 TGSI_OPCODE_DSSG = 222, 581 582 TGSI_OPCODE_VOTE_ANY = 223, 583 TGSI_OPCODE_VOTE_ALL = 224, 584 TGSI_OPCODE_VOTE_EQ = 225, 585 586 TGSI_OPCODE_U64SEQ = 226, 587 TGSI_OPCODE_U64SNE = 227, 588 TGSI_OPCODE_I64SLT = 228, 589 TGSI_OPCODE_U64SLT = 229, 590 TGSI_OPCODE_I64SGE = 230, 591 TGSI_OPCODE_U64SGE = 231, 592 593 TGSI_OPCODE_I64MIN = 232, 594 TGSI_OPCODE_U64MIN = 233, 595 TGSI_OPCODE_I64MAX = 234, 596 TGSI_OPCODE_U64MAX = 235, 597 598 TGSI_OPCODE_I64ABS = 236, 599 TGSI_OPCODE_I64SSG = 237, 600 TGSI_OPCODE_I64NEG = 238, 601 602 TGSI_OPCODE_U64ADD = 239, 603 TGSI_OPCODE_U64MUL = 240, 604 TGSI_OPCODE_U64SHL = 241, 605 TGSI_OPCODE_I64SHR = 242, 606 TGSI_OPCODE_U64SHR = 243, 607 608 TGSI_OPCODE_I64DIV = 244, 609 TGSI_OPCODE_U64DIV = 245, 610 TGSI_OPCODE_I64MOD = 246, 611 TGSI_OPCODE_U64MOD = 247, 612 613 TGSI_OPCODE_DDIV = 248, 614 615 TGSI_OPCODE_LOD = 249, 616 617 TGSI_OPCODE_ATOMINC_WRAP = 250, 618 TGSI_OPCODE_ATOMDEC_WRAP = 251, 619 620 TGSI_OPCODE_LAST = 252, 621 }; 622 623 624 /** 625 * Opcode is the operation code to execute. A given operation defines the 626 * semantics how the source registers (if any) are interpreted and what is 627 * written to the destination registers (if any) as a result of execution. 628 * 629 * NumDstRegs and NumSrcRegs is the number of destination and source registers, 630 * respectively. For a given operation code, those numbers are fixed and are 631 * present here only for convenience. 632 * 633 * Saturate controls how are final results in destination registers modified. 634 */ 635 636 struct tgsi_instruction 637 { 638 unsigned Type : 4; /* TGSI_TOKEN_TYPE_INSTRUCTION */ 639 unsigned NrTokens : 8; /* UINT */ 640 unsigned Opcode : 8; /* TGSI_OPCODE_ */ 641 unsigned Saturate : 1; /* BOOL */ 642 unsigned NumDstRegs : 2; /* UINT */ 643 unsigned NumSrcRegs : 4; /* UINT */ 644 unsigned Label : 1; 645 unsigned Texture : 1; 646 unsigned Memory : 1; 647 unsigned Precise : 1; 648 unsigned Padding : 1; 649 }; 650 651 /* 652 * If tgsi_instruction::Label is TRUE, tgsi_instruction_label follows. 653 * 654 * If tgsi_instruction::Texture is TRUE, tgsi_instruction_texture follows. 655 * if texture instruction has a number of offsets, 656 * then tgsi_instruction::Texture::NumOffset of tgsi_texture_offset follow. 657 * 658 * Then, tgsi_instruction::NumDstRegs of tgsi_dst_register follow. 659 * 660 * Then, tgsi_instruction::NumSrcRegs of tgsi_src_register follow. 661 * 662 * tgsi_instruction::NrTokens contains the total number of words that make the 663 * instruction, including the instruction word. 664 */ 665 666 enum tgsi_swizzle { 667 TGSI_SWIZZLE_X, 668 TGSI_SWIZZLE_Y, 669 TGSI_SWIZZLE_Z, 670 TGSI_SWIZZLE_W, 671 }; 672 673 struct tgsi_instruction_label 674 { 675 unsigned Label : 24; /* UINT */ 676 unsigned Padding : 8; 677 }; 678 679 enum tgsi_texture_type { 680 TGSI_TEXTURE_BUFFER, 681 TGSI_TEXTURE_1D, 682 TGSI_TEXTURE_2D, 683 TGSI_TEXTURE_3D, 684 TGSI_TEXTURE_CUBE, 685 TGSI_TEXTURE_RECT, 686 TGSI_TEXTURE_SHADOW1D, 687 TGSI_TEXTURE_SHADOW2D, 688 TGSI_TEXTURE_SHADOWRECT, 689 TGSI_TEXTURE_1D_ARRAY, 690 TGSI_TEXTURE_2D_ARRAY, 691 TGSI_TEXTURE_SHADOW1D_ARRAY, 692 TGSI_TEXTURE_SHADOW2D_ARRAY, 693 TGSI_TEXTURE_SHADOWCUBE, 694 TGSI_TEXTURE_2D_MSAA, 695 TGSI_TEXTURE_2D_ARRAY_MSAA, 696 TGSI_TEXTURE_CUBE_ARRAY, 697 TGSI_TEXTURE_SHADOWCUBE_ARRAY, 698 TGSI_TEXTURE_UNKNOWN, 699 TGSI_TEXTURE_COUNT, 700 }; 701 702 struct tgsi_instruction_texture 703 { 704 unsigned Texture : 8; /* TGSI_TEXTURE_ */ 705 unsigned NumOffsets : 4; 706 unsigned ReturnType : 3; /* TGSI_RETURN_TYPE_x */ 707 unsigned Padding : 17; 708 }; 709 710 /* for texture offsets in GLSL and DirectX. 711 * Generally these always come from TGSI_FILE_IMMEDIATE, 712 * however DX11 appears to have the capability to do 713 * non-constant texture offsets. 714 */ 715 struct tgsi_texture_offset 716 { 717 int Index : 16; 718 unsigned File : 4; /**< one of TGSI_FILE_x */ 719 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_x */ 720 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_x */ 721 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_x */ 722 unsigned Padding : 6; 723 }; 724 725 /** 726 * File specifies the register array to access. 727 * 728 * Index specifies the element number of a register in the register file. 729 * 730 * If Indirect is TRUE, Index should be offset by the X component of the indirect 731 * register that follows. The register can be now fetched into local storage 732 * for further processing. 733 * 734 * If Negate is TRUE, all components of the fetched register are negated. 735 * 736 * The fetched register components are swizzled according to SwizzleX, SwizzleY, 737 * SwizzleZ and SwizzleW. 738 * 739 */ 740 741 struct tgsi_src_register 742 { 743 unsigned File : 4; /* TGSI_FILE_ */ 744 unsigned Indirect : 1; /* BOOL */ 745 unsigned Dimension : 1; /* BOOL */ 746 int Index : 16; /* SINT */ 747 unsigned SwizzleX : 2; /* TGSI_SWIZZLE_ */ 748 unsigned SwizzleY : 2; /* TGSI_SWIZZLE_ */ 749 unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_ */ 750 unsigned SwizzleW : 2; /* TGSI_SWIZZLE_ */ 751 unsigned Absolute : 1; /* BOOL */ 752 unsigned Negate : 1; /* BOOL */ 753 }; 754 755 /** 756 * If tgsi_src_register::Indirect is TRUE, tgsi_ind_register follows. 757 * 758 * File, Index and Swizzle are handled the same as in tgsi_src_register. 759 * 760 * If ArrayID is zero the whole register file might be indirectly addressed, 761 * if not only the Declaration with this ArrayID is accessed by this operand. 762 * 763 */ 764 765 struct tgsi_ind_register 766 { 767 unsigned File : 4; /* TGSI_FILE_ */ 768 int Index : 16; /* SINT */ 769 unsigned Swizzle : 2; /* TGSI_SWIZZLE_ */ 770 unsigned ArrayID : 10; /* UINT */ 771 }; 772 773 /** 774 * If tgsi_src_register::Dimension is TRUE, tgsi_dimension follows. 775 */ 776 777 struct tgsi_dimension 778 { 779 unsigned Indirect : 1; /* BOOL */ 780 unsigned Dimension : 1; /* BOOL */ 781 unsigned Padding : 14; 782 int Index : 16; /* SINT */ 783 }; 784 785 struct tgsi_dst_register 786 { 787 unsigned File : 4; /* TGSI_FILE_ */ 788 unsigned WriteMask : 4; /* TGSI_WRITEMASK_ */ 789 unsigned Indirect : 1; /* BOOL */ 790 unsigned Dimension : 1; /* BOOL */ 791 int Index : 16; /* SINT */ 792 unsigned Padding : 6; 793 }; 794 795 #define TGSI_MEMORY_COHERENT (1 << 0) 796 #define TGSI_MEMORY_RESTRICT (1 << 1) 797 #define TGSI_MEMORY_VOLATILE (1 << 2) 798 /* The "stream" cache policy will minimize memory cache usage if other 799 * memory operations need the cache. 800 */ 801 #define TGSI_MEMORY_STREAM_CACHE_POLICY (1 << 3) 802 803 /** 804 * Specifies the type of memory access to do for the LOAD/STORE instruction. 805 */ 806 struct tgsi_instruction_memory 807 { 808 unsigned Qualifier : 4; /* TGSI_MEMORY_ */ 809 unsigned Texture : 8; /* only for images: TGSI_TEXTURE_ */ 810 unsigned Format : 10; /* only for images: PIPE_FORMAT_ */ 811 unsigned Padding : 10; 812 }; 813 814 #define TGSI_MEMBAR_SHADER_BUFFER (1 << 0) 815 #define TGSI_MEMBAR_ATOMIC_BUFFER (1 << 1) 816 #define TGSI_MEMBAR_SHADER_IMAGE (1 << 2) 817 #define TGSI_MEMBAR_SHARED (1 << 3) 818 #define TGSI_MEMBAR_THREAD_GROUP (1 << 4) 819 820 #ifdef __cplusplus 821 } 822 #endif 823 824 #endif /* P_SHADER_TOKENS_H */ 825