1 /* 2 * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 #if !defined (__GFX9_GB_REG_H__) 28 #define __GFX9_GB_REG_H__ 29 30 /* 31 * gfx9_gb_reg.h 32 * 33 * Register Spec Release: 1.0 34 * 35 */ 36 37 // 38 // Make sure the necessary endian defines are there. 39 // 40 #if defined(LITTLEENDIAN_CPU) 41 #elif defined(BIGENDIAN_CPU) 42 #else 43 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 44 #endif 45 46 union GB_ADDR_CONFIG_GFX9 { 47 struct { 48 #if defined(LITTLEENDIAN_CPU) 49 unsigned int NUM_PIPES : 3; 50 unsigned int PIPE_INTERLEAVE_SIZE : 3; 51 unsigned int MAX_COMPRESSED_FRAGS : 2; 52 unsigned int BANK_INTERLEAVE_SIZE : 3; 53 unsigned int : 1; 54 unsigned int NUM_BANKS : 3; 55 unsigned int : 1; 56 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 57 unsigned int NUM_SHADER_ENGINES : 2; 58 unsigned int NUM_GPUS : 3; 59 unsigned int MULTI_GPU_TILE_SIZE : 2; 60 unsigned int NUM_RB_PER_SE : 2; 61 unsigned int ROW_SIZE : 2; 62 unsigned int NUM_LOWER_PIPES : 1; 63 unsigned int SE_ENABLE : 1; 64 #elif defined(BIGENDIAN_CPU) 65 unsigned int SE_ENABLE : 1; 66 unsigned int NUM_LOWER_PIPES : 1; 67 unsigned int ROW_SIZE : 2; 68 unsigned int NUM_RB_PER_SE : 2; 69 unsigned int MULTI_GPU_TILE_SIZE : 2; 70 unsigned int NUM_GPUS : 3; 71 unsigned int NUM_SHADER_ENGINES : 2; 72 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 73 unsigned int : 1; 74 unsigned int NUM_BANKS : 3; 75 unsigned int : 1; 76 unsigned int BANK_INTERLEAVE_SIZE : 3; 77 unsigned int MAX_COMPRESSED_FRAGS : 2; 78 unsigned int PIPE_INTERLEAVE_SIZE : 3; 79 unsigned int NUM_PIPES : 3; 80 #endif 81 } bitfields, bits; 82 unsigned int u32All; 83 signed int i32All; 84 float f32All; 85 }; 86 87 #endif 88 89