Searched refs:AMDGPU_IRQ_STATE_DISABLE (Results 1 – 24 of 24) sorted by relevance
42 AMDGPU_IRQ_STATE_DISABLE, enumerator
130 AMDGPU_IRQ_STATE_DISABLE); in amdgpu_irq_disable_all()475 state = AMDGPU_IRQ_STATE_DISABLE; in amdgpu_irq_update()
597 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()613 case AMDGPU_IRQ_STATE_DISABLE: in si_dma_set_trap_irq_state()
1014 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()1030 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v2_4_set_trap_irq_state()
1118 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()1134 case AMDGPU_IRQ_STATE_DISABLE: in cik_sdma_set_trap_irq_state()
252 amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; in dce_virtual_crtc_init()
432 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_ecc_interrupt_state()484 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v9_0_vm_fault_interrupt_state()
1348 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()1364 case AMDGPU_IRQ_STATE_DISABLE: in sdma_v3_0_set_trap_irq_state()
2899 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vblank_interrupt_state()2950 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_crtc_vline_interrupt_state()2978 case AMDGPU_IRQ_STATE_DISABLE: in dce_v8_0_set_hpd_interrupt_state()3093 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v8_0_set_pageflip_interrupt_state()
1049 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v6_0_vm_fault_interrupt_state()
3240 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_gfx_eop_interrupt_state()3261 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_compute_eop_interrupt_state()3303 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_reg_fault_state()3328 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v6_0_set_priv_inst_fault_state()
2987 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vblank_interrupt_state()3016 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_crtc_vline_interrupt_state()3046 case AMDGPU_IRQ_STATE_DISABLE: in dce_v10_0_set_hpd_irq_state()3124 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v10_0_set_pageflip_irq_state()
73 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v10_0_vm_fault_interrupt_state()
3113 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vblank_interrupt_state()3142 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_crtc_vline_interrupt_state()3172 case AMDGPU_IRQ_STATE_DISABLE: in dce_v11_0_set_hpd_irq_state()3250 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v11_0_set_pageflip_irq_state()
2853 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_crtc_vblank_interrupt_state()2888 case AMDGPU_IRQ_STATE_DISABLE: in dce_v6_0_set_hpd_interrupt_state()3003 if (state == AMDGPU_IRQ_STATE_DISABLE) in dce_v6_0_set_pageflip_interrupt_state()
4726 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_gfx_eop_interrupt_state()4777 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_compute_eop_interrupt_state()4800 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_reg_fault_state()4825 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v7_0_set_priv_inst_fault_state()
6442 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_gfx_eop_interrupt_state()6481 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_compute_eop_interrupt_state()6502 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_reg_fault_state()6513 state == AMDGPU_IRQ_STATE_DISABLE ? 0 : 1); in gfx_v8_0_set_priv_inst_fault_state()6565 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_cp_ecc_int_state()6610 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v8_0_set_sq_int_state()
1241 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v7_0_vm_fault_interrupt_state()
5642 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_gfx_eop_interrupt_state()5689 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_compute_eop_interrupt_state()5712 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_reg_fault_state()5731 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_priv_inst_fault_state()5757 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v9_0_set_cp_ecc_error_state()
1419 case AMDGPU_IRQ_STATE_DISABLE: in gmc_v8_0_vm_fault_interrupt_state()
8231 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_gfx_eop_interrupt_state()8284 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_compute_eop_interrupt_state()8384 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_priv_reg_fault_state()8403 case AMDGPU_IRQ_STATE_DISABLE: in gfx_v10_0_set_priv_inst_fault_state()8483 if (state == AMDGPU_IRQ_STATE_DISABLE) { in gfx_v10_0_kiq_set_interrupt_state()
3148 case AMDGPU_IRQ_STATE_DISABLE: in kv_dpm_set_interrupt_state()3165 case AMDGPU_IRQ_STATE_DISABLE: in kv_dpm_set_interrupt_state()
7514 case AMDGPU_IRQ_STATE_DISABLE: in si_dpm_set_interrupt_state()7531 case AMDGPU_IRQ_STATE_DISABLE: in si_dpm_set_interrupt_state()
1253 case AMDGPU_IRQ_STATE_DISABLE: in smu_v11_0_set_irq_state()