Searched refs:CACHELINE_BYTES (Results 1 – 13 of 13) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | intel_ring_types.h | 20 #define CACHELINE_BYTES 64 macro
21 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
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| D | intel_ring.h | 110 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid()
138 return (head - tail - CACHELINE_BYTES) & (size - 1); in __intel_ring_space()
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| D | intel_timeline.c | 54 BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE); in hwsp_alloc()
248 timeline->hwsp_offset = cacheline * CACHELINE_BYTES; in intel_timeline_init()
259 memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES); in intel_timeline_init()
520 tl->hwsp_offset = cacheline * CACHELINE_BYTES; in __intel_timeline_get_seqno()
522 memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES); in __intel_timeline_get_seqno()
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| D | intel_ring.c | 161 ring->effective_size -= 2 * CACHELINE_BYTES; in intel_engine_create_ring()
307 num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32); in intel_ring_cacheline_align()
321 GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1)); in intel_ring_cacheline_align()
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| D | intel_engine.h | 29 #define CACHELINE_BYTES 64 macro
30 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
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| D | selftest_timeline.c | 36 return (address + tl->hwsp_offset) / CACHELINE_BYTES; in hwsp_cacheline()
39 #define CACHELINES_PER_PAGE (PAGE_SIZE / CACHELINE_BYTES)
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| D | intel_lrc.c | 340 GEM_BUG_ON(!IS_ALIGNED(size, CACHELINE_BYTES)); in lrc_ring_setup_indirect_ctx()
343 ctx_bb_ggtt_addr | (size / CACHELINE_BYTES); in lrc_ring_setup_indirect_ctx()
3444 while ((unsigned long)cs % CACHELINE_BYTES) in setup_indirect_ctx_bb()
3769 while ((unsigned long)batch % CACHELINE_BYTES) in gen8_init_indirectctx_bb()
3866 while ((unsigned long)batch % CACHELINE_BYTES) in gen9_init_indirectctx_bb()
3900 while ((unsigned long)batch % CACHELINE_BYTES) in gen10_init_indirectctx_bb()
3998 CACHELINE_BYTES))) { in intel_init_workaround_bb()
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| /kernel/linux/linux-5.10/arch/powerpc/lib/ |
| D | string_32.S | 16 CACHELINE_BYTES = L1_CACHE_BYTES define
51 addi r6, r6, CACHELINE_BYTES
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| D | checksum_32.S | 123 CACHELINE_BYTES = L1_CACHE_BYTES define
183 addi r3,r3,CACHELINE_BYTES
187 addi r3,r3,CACHELINE_BYTES
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| D | copy_32.S | 64 CACHELINE_BYTES = L1_CACHE_BYTES define
127 addi r6,r6,CACHELINE_BYTES
377 addi r3,r3,CACHELINE_BYTES
381 addi r3,r3,CACHELINE_BYTES
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dsb.c | 226 tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); in intel_dsb_commit()
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| D | scheduler.c | 586 0, CACHELINE_BYTES, 0); in prepare_shadow_wa_ctx()
598 memset(per_ctx_va, 0, CACHELINE_BYTES); in prepare_shadow_wa_ctx()
1668 CACHELINE_BYTES; in intel_vgpu_create_workload()
1687 CACHELINE_BYTES)) { in intel_vgpu_create_workload()
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| D | cmd_parser.c | 2852 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES, in scan_wa_ctx()
2971 roundup(ctx_size + CACHELINE_BYTES, in shadow_indirect_ctx()
3026 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES); in combine_wa_ctx()
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