Searched refs:CIU_REG (Results 1 – 5 of 5) sorted by relevance
64 __raw_writel(0x0, CIU_REG(0x64)); in pm_scu_clk_disable()65 __raw_writel(0x0, CIU_REG(0x68)); in pm_scu_clk_disable()68 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_disable()70 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_disable()80 __raw_writel(0x03003003, CIU_REG(0x64)); in pm_scu_clk_enable()81 __raw_writel(0x00303030, CIU_REG(0x68)); in pm_scu_clk_enable()84 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_enable()86 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_enable()237 __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); in mmp2_pm_init()
10 #define SW_BRANCH_VIRT_ADDR CIU_REG(0x24)
204 while (!(readl(CIU_REG(0x8)) & (1 << 16))) in pxa910_pm_enter()212 while (!(readl(CIU_REG(0x8)) & (1 << 16))) in pxa910_pm_enter()
43 #define CIU_REG(x) (CIU_VIRT_BASE + (x)) macro
20 #define MMP_CHIPID CIU_REG(0x00)