Searched refs:CLIDR (Results 1 – 2 of 2) sorted by relevance
95 #define CLIDR CP15_REG(c0, 1, c0, 1) /* Cache Level ID Register */ macro
929 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"934 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR