Searched refs:CLK_RESET_PLLX_BASE (Results 1 – 2 of 2) sorted by relevance
56 #define CLK_RESET_PLLX_BASE 0xe0 macro351 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0383 pll_locked r1, r0, CLK_RESET_PLLX_BASE666 ldr r0, [r5, #CLK_RESET_PLLX_BASE]668 str r0, [r5, #CLK_RESET_PLLX_BASE]
122 #define CLK_RESET_PLLX_BASE 0xe0 macro1152 readl(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_suspend()1177 base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()1185 clk_base + CLK_RESET_PLLX_BASE); in tegra30_cpu_clock_resume()