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Searched refs:CLK_TOP_HDCP_SEL (Results 1 – 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dmt8173-clk.h128 #define CLK_TOP_HDCP_SEL 118 macro
Dmt2712-clk.h166 #define CLK_TOP_HDCP_SEL 135 macro
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt8173.c591 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x00d0, 8, 2, 15),
Dclk-mt2712.c819 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",