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Searched refs:CLK_TOP_SPISLV_SEL (Results 1 – 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt13 - assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
30 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
/kernel/linux/linux-5.10/include/dt-bindings/clock/
Dmt2712-clk.h188 #define CLK_TOP_SPISLV_SEL 157 macro
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt2712.c868 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
/kernel/linux/linux-5.10/arch/arm64/boot/dts/mediatek/
Dmt2712e.dtsi321 assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;