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Searched refs:CRTC (Results 1 – 25 of 43) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
Dcrtc.c60 crtcstate->CRTC[index]); in crtc_wr_cio_state()
69 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
72 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
345 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; in nv_crtc_mode_set_vga()
346 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; in nv_crtc_mode_set_vga()
347 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; in nv_crtc_mode_set_vga()
348 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | in nv_crtc_mode_set_vga()
350 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; in nv_crtc_mode_set_vga()
351 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | in nv_crtc_mode_set_vga()
[all …]
Dcursor.c34 crtcstate->CRTC[index]); in crtc_wr_cio_state()
45 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = in nv04_cursor_set_offset()
48 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = in nv04_cursor_set_offset()
51 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= in nv04_cursor_set_offset()
53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; in nv04_cursor_set_offset()
Dtvnv04.c112 state->CRTC[NV_CIO_CRE_49] |= 0x10; in nv04_tv_bind()
114 state->CRTC[NV_CIO_CRE_49] &= ~0x10; in nv04_tv_bind()
117 state->CRTC[NV_CIO_CRE_LCD__INDEX]); in nv04_tv_bind()
119 state->CRTC[NV_CIO_CRE_49]); in nv04_tv_bind()
Ddisp.h23 uint8_t CRTC[0xa0]; member
Ddfp.c109 crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= in nv04_dfp_disable()
252 uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
253 uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; in nv04_dfp_prepare()
Dtvnv17.c403 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ in nv17_tv_prepare()
469 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ in nv17_tv_mode_set()
470 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ in nv17_tv_mode_set()
Dhw.h376 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; in nv_show_cursor()
/kernel/linux/linux-5.10/drivers/video/fbdev/matrox/
Dmatroxfb_misc.c304 hw->CRTC[0] = ht-4; in matroxfb_vgaHWinit()
305 hw->CRTC[1] = hd; in matroxfb_vgaHWinit()
306 hw->CRTC[2] = hd; in matroxfb_vgaHWinit()
307 hw->CRTC[3] = (hbe & 0x1F) | 0x80; in matroxfb_vgaHWinit()
308 hw->CRTC[4] = hs; in matroxfb_vgaHWinit()
309 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F); in matroxfb_vgaHWinit()
310 hw->CRTC[6] = vt & 0xFF; in matroxfb_vgaHWinit()
311 hw->CRTC[7] = ((vt & 0x100) >> 8) | in matroxfb_vgaHWinit()
319 hw->CRTC[8] = 0x00; in matroxfb_vgaHWinit()
320 hw->CRTC[9] = ((vd & 0x200) >> 4) | in matroxfb_vgaHWinit()
[all …]
Dmatroxfb_base.h270 unsigned char CRTC[25]; member
/kernel/linux/linux-5.10/drivers/video/fbdev/
Dneofb.c283 par->CRTC[0] = htotal - 5; in vgaHWInit()
284 par->CRTC[1] = (var->xres >> 3) - 1; in vgaHWInit()
285 par->CRTC[2] = (var->xres >> 3) - 1; in vgaHWInit()
286 par->CRTC[3] = ((htotal - 1) & 0x1F) | 0x80; in vgaHWInit()
287 par->CRTC[4] = ((var->xres + var->right_margin) >> 3); in vgaHWInit()
288 par->CRTC[5] = (((htotal - 1) & 0x20) << 2) in vgaHWInit()
290 par->CRTC[6] = (vtotal - 2) & 0xFF; in vgaHWInit()
291 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8) in vgaHWInit()
298 par->CRTC[8] = 0x00; in vgaHWInit()
299 par->CRTC[9] = (((var->yres - 1) & 0x200) >> 4) | 0x40; in vgaHWInit()
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/savage/
Dsavagefb_driver.c127 VGAwCR(17, reg->CRTC[17] & ~0x80, par); in vgaHWRestore()
130 VGAwCR(i, reg->CRTC[i], par); in vgaHWRestore()
168 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5; in vgaHWInit()
169 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1; in vgaHWInit()
170 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1; in vgaHWInit()
171 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80; in vgaHWInit()
172 reg->CRTC[0x04] = (timings->HSyncStart >> 3); in vgaHWInit()
173 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) | in vgaHWInit()
175 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF; in vgaHWInit()
176 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) | in vgaHWInit()
[all …]
Dsavagefb.h155 unsigned char CRTC[25]; /* Crtc Controller */ member
/kernel/linux/linux-5.10/Documentation/gpu/
Dkms-properties.csv61 armada,CRTC,"""CSC_YUV""",ENUM,"{ ""Auto"" , ""CCIR601"", ""CCIR709"" }",CRTC,TBD
62 ,,"""CSC_RGB""",ENUM,"{ ""Auto"", ""Computer system"", ""Studio"" }",CRTC,TBD
72 exynos,CRTC,“mode”,ENUM,"{ ""normal"", ""blank"" }",CRTC,TBD
90 omap,Generic,“zorder”,RANGE,"Min=0, Max=3","CRTC, Plane",TBD
Ddrm-kms.rst61 details. One or more (or even no) planes feed their pixel data into a CRTC
62 (represented by :c:type:`struct drm_crtc <drm_crtc>`, see `CRTC Abstraction`_)
70 to figure out which connections between a CRTC and a connector are possible, and
75 A CRTC can be connected to multiple encoders, and for an active CRTC there must
140 the CRTC and any encoders. Often for drivers with bridges there's no code left
307 CRTC Abstraction
313 CRTC Functions Reference
463 Standard CRTC Properties
467 :doc: standard CRTC properties
Dvc4.rst15 Pixel Valve (DRM CRTC)
19 :doc: VC4 CRTC module
Ddrm-kms-helpers.rst20 helpers. Old drivers still often use the legacy CRTC helpers. They both share
406 Legacy CRTC/Modeset Helper Functions Reference
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.h104 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\
105 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\
111 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
116 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
122 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
127 HWSEQ_PIXEL_RATE_REG_LIST(CRTC)
139 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \
149 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
150 HWSEQ_PHYPLL_REG_LIST(CRTC), \
162 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \
[all …]
Ddce_transform.h99 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
103 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
104 SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
164 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
170 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
Ddce_ipp.h58 SRI(DCFE_MEM_PWR_CTRL, CRTC, id)
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c147 IRQ_REG_ENTRY(CRTC, reg_num,\
155 IRQ_REG_ENTRY(CRTC, reg_num,\
/kernel/linux/linux-5.10/drivers/usb/misc/sisusbvga/
Dsisusb_struct.h74 unsigned char CRTC[0x19]; member
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/armada/
Dmarvell,dove-lcd.txt1 Device Tree bindings for Armada DRM CRTC driver
/kernel/linux/linux-5.10/include/video/
Dneomagic.h129 unsigned char CRTC[25]; /* Crtc Controller */ member
/kernel/linux/linux-5.10/drivers/gpu/drm/sti/
DNOTES47 FB & planes Cursor CRTC Encoders Bridges/Connectors
/kernel/linux/linux-5.10/drivers/video/fbdev/sis/
Dvstruct.h136 unsigned char CRTC[0x19]; member

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