Searched refs:DCLK (Results 1 – 13 of 13) sorted by relevance
144 uint32_t DCLK; member
62 intel_uncore_read(llc_to_gt(llc)->uncore, DCLK) & 0xf; in get_ia_constants()
99 58: 3DCLK
220 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */
763 ps->uvd_clocks.DCLK = le32_to_cpu(pnon_clock_info->ulDCLK); in init_non_clock_fields()766 ps->uvd_clocks.DCLK = 0; in init_non_clock_fields()
850 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu10_dpm_get_pp_table_entry()
3262 power_state->uvd_clocks.DCLK = 0; in smu7_get_pp_table_entry_callback_func_v1()3355 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v1()3503 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in smu7_get_pp_table_entry_v0()
1416 smu8_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; in smu8_dpm_get_pp_table_entry()
3141 power_state->uvd_clocks.DCLK = 0; in vega10_get_pp_table_entry_callback_func()3219 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
154 CLK_MAP(DCLK, PPCLK_DCLK),
155 CLK_MAP(DCLK, PPCLK_DCLK),
139 CLK_MAP(DCLK, PPCLK_DCLK_0),
3760 #define DCLK _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5e04) macro