Searched refs:DC__VOLTAGE_STATES (Results 1 – 7 of 7) sorted by relevance
364 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];365 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];413 double DCFCLKPerState[DC__VOLTAGE_STATES];414 double DCFCLKState[DC__VOLTAGE_STATES][2];415 double FabricClockPerState[DC__VOLTAGE_STATES];416 double SOCCLKPerState[DC__VOLTAGE_STATES];417 double PHYCLKPerState[DC__VOLTAGE_STATES];418 double DTBCLKPerState[DC__VOLTAGE_STATES];419 double MaxDppclk[DC__VOLTAGE_STATES];420 double MaxDSCCLK[DC__VOLTAGE_STATES];[all …]
32 #define DC__VOLTAGE_STATES 9 macro
73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
2439 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2440 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2441 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2442 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box()2444 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; in dcn30_update_bw_bounding_box()2521 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2535 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()2540 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && in dcn30_update_bw_bounding_box()
1406 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; in update_bw_bounding_box()
3489 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
6720 double TotalMaxPrefetchFlipDPTERowBandwidth[DC__VOLTAGE_STATES][2] = { { 0 } }; in UseMinimumDCFCLK()