| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
|
| D | sddr2.c | 63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
|
| D | sddr3.c | 72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
|
| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
|
| D | sram242x.S | 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
|
| D | sram243x.S | 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
|
| /kernel/linux/linux-5.10/arch/x86/boot/ |
| D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
109 dll = inb(port + DLL); in probe_baud()
|
| /kernel/linux/linux-5.10/tools/testing/kunit/ |
| D | .gitignore | 2 # Byte-compiled / optimized / DLL files
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/ |
| D | rk3399_dmc.txt | 62 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
64 DDR3 DLL will be bypassed. Note: if DLL was bypassed,
69 DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
70 Note: PHY DLL and PHY ODT are independent.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-sprd.txt | 26 PHY DLL delays are used to delay the data valid window, and align the window
27 to sampling clock. PHY DLL delays can be configured by following properties,
|
| D | sdhci-st.txt | 27 to configure DLL inside the flashSS, if so reg-names must also be
32 for eMMC on stih407 family silicon to configure DLL inside FlashSS.
|
| /kernel/linux/linux-5.10/arch/arm/mach-orion5x/ |
| D | tsx09-common.c | 33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
|
| D | terastation_pro2-setup.c | 276 writel(divisor & 0xff, UART1_REG(DLL)); in tsp2_power_off()
|
| D | kurobox_pro-setup.c | 301 writel(divisor & 0xff, UART1_REG(DLL)); in kurobox_pro_power_off()
|
| /kernel/linux/linux-5.10/drivers/usb/serial/ |
| D | io_16654.h | 40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB macro
|
| D | io_edgeport.c | 2336 MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, DLL, LOW8(divisor)); in send_cmd_write_baud_rate()
|
| /kernel/linux/linux-5.10/arch/x86/kernel/ |
| D | early_printk.c | 94 #define DLL 0 /* Divisor Latch Low */ macro
141 serial_out(early_serial_base, DLL, divisor & 0xff); in early_serial_hw_init()
|
| /kernel/linux/linux-5.10/drivers/power/reset/ |
| D | qnap-poweroff.c | 62 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_power_off()
|
| /kernel/linux/linux-5.10/drivers/net/hamradio/ |
| D | baycom_ser_fdx.c | 102 #define DLL(iobase) (iobase+0) macro
174 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
|
| D | baycom_ser_hdx.c | 88 #define DLL(iobase) (iobase+0) macro
159 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
|
| D | yam.c | 159 #define DLL(iobase) (iobase+0) macro
295 outb(1, DLL(iobase)); in fpga_reset()
467 outb(divisor, DLL(dev->base_addr)); in yam_set_uart()
|
| /kernel/linux/patches/linux-5.10/imx8mm_patch/patches/drivers/ |
| D | 0030_linux_drivers_pci_misc_nvmem_of_mtd_mmc.patch | 8509 - /* DLL is only required for HS400 */
10213 /* DLL Config 0 Register */
10219 /* DLL Config 1 Register */
10522 - * Configure DLL user control register to enable DLL status.
10579 - * starts coming. Controllers with 14lpp and later tech DLL cannot
10581 - * turned on for host controllers using this DLL.
10595 * Drain writebuffer to ensure above DLL calibration
11074 - "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
11079 - "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
11308 * restore the SDR DLL settings when the clock is ungated.
[all …]
|
| /kernel/linux/patches/linux-4.19/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 315558 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
315609 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
315640 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
315660 + pr_err("%s: DS 180 DLL master not ready.\n", mmc_hostname(host->mmc));
316233 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
316284 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
316315 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
316335 + pr_err("%s: DS 180 DLL master not ready.\n", mmc_hostname(host->mmc));
316913 + pr_err("%s: DRV DLL master not locked.\n", mmc_hostname(host->mmc));
316964 + pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc));
[all …]
|
| /kernel/linux/patches/linux-5.10/yangfan_patch/ |
| D | drivers.patch | 43841 + /* Disable DLL and reset both of sample and drive clock */
43848 + /* Reset DLL */
43862 + /* Init DLL settings */
43871 + dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n");
|