Searched refs:DMA_RESET (Results 1 – 14 of 14) sorted by relevance
| /kernel/linux/linux-5.10/include/linux/ |
| D | rtsx_usb.h | 576 #define DMA_RESET 0x01 macro
615 rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET); in rtsx_usb_clear_dma_err()
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| /kernel/linux/linux-5.10/include/dt-bindings/reset/ |
| D | altr,rst-mgr-s10.h | 35 #define DMA_RESET 48 macro
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| D | altr,rst-mgr.h | 45 #define DMA_RESET 60 macro
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| D | altr,rst-mgr-a10.h | 32 #define DMA_RESET 48 macro
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| /kernel/linux/linux-5.10/arch/mips/lantiq/xway/ |
| D | dma.c | 39 #define DMA_RESET BIT(0) /* channel on / off bit */ macro
228 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); in ltq_dma_init()
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | dvma.h | 224 #define DMA_RESET(dma) do { \ macro
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 343 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 340 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
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| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| D | ni_pcidio.c | 82 #define DMA_RESET BIT(6) macro
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | socfpga.dtsi | 87 resets = <&rst DMA_RESET>;
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| D | socfpga_arria10.dtsi | 71 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
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| /kernel/linux/linux-5.10/drivers/scsi/ |
| D | FlashPoint.c | 580 #define DMA_RESET BIT(3) macro
6446 WR_HARPOON(port + hp_scsireset, (DMA_RESET | HPSCSI_RESET | PROG_RESET | in FPT_XbowInit()
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| /kernel/linux/patches/linux-5.10/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 25847 + reg_value |= CTRL_RESET | FIFO_RESET | DMA_RESET;
26205 + regval |= CTRL_RESET | FIFO_RESET | DMA_RESET;
28121 + val |= CTRL_RESET | FIFO_RESET | DMA_RESET;
29002 +#define DMA_RESET (1 << 2)
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| /kernel/linux/patches/linux-4.19/hispark_taurus_patch/ |
| D | hispark_taurus.patch | 310829 + reg_value |= CTRL_RESET | FIFO_RESET | DMA_RESET;
311187 + regval |= CTRL_RESET | FIFO_RESET | DMA_RESET;
313105 + val |= CTRL_RESET | FIFO_RESET | DMA_RESET;
314750 +#define DMA_RESET (1 << 2)
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