Searched refs:DMB (Results 1 – 12 of 12) sorted by relevance
52 DMB; in OsSavePte1()119 DMB; in OsSavePte2()131 DMB; in OsSavePte2Continuous()147 DMB; in OsClearPte2Continuous()
52 #define DMB __asm__ volatile("dmb" ::: "memory") macro
17 * - Conexant DMB-TH Stick39 * - Mygica D689 DMB-TH
106 - Mygica X8506 DMB-TH126 - Mygica X8558 PRO DMB-TH
201 atbm8830 AltoBeam ATBM8830/8831 DMB-TH demodulator210 lgs8gxx Legend Silicon LGS8913/LGS8GL5/LGS8GXX DMB-TH demodulator
758 - MagicPro ProHDTV Pro2 DMB-TH/Hybrid
114 DMB; in LockVdsoDataPage()119 DMB; in UnlockVdsoDataPage()
101 bl vlock_trylock @ implies DMB163 bl vlock_unlock @ implies DMB
63 voting_end r0, r1, r2 @ implies DMB
859 A DMB-TH tuner module. Say Y when you want to support this frontend.862 tristate "Legend Silicon LGS8913/LGS8GL5/LGS8GXX DMB-TH demodulator"867 A DMB-TH tuner module. Say Y when you want to support this frontend.870 tristate "AltoBeam ATBM8830/8831 DMB-TH demodulator"874 A DMB-TH tuner module. Say Y when you want to support this frontend.
836 or Data Memory Barrier (DMB) command immediately after the WFI/WFE901 bool "ARM errata: DMB operation may be faulty"906 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction909 the diagnostic register of the Cortex-A9 which causes the DMB1078 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"1083 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable1095 bool "ARM errata: A17: DMB ST might fail to create order between stores"1100 execution of a DMB ST instruction might fail to properly order
660 Work around the issue by inserting DMB SY barriers around PAR_EL1661 register reads and warning KVM users. The DMB barrier is sufficient1342 strongly recommended to use the ISB, DSB, and DMB