Searched refs:FW_BLC_SELF (Results 1 – 5 of 5) sorted by relevance
471 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()474 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()475 REG_READ(FW_BLC_SELF); in cdv_disable_sr()534 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); in cdv_update_wm()535 REG_READ(FW_BLC_SELF); in cdv_update_wm()
598 #define FW_BLC_SELF 0x20e0 macro
372 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()373 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in _intel_set_memory_cxsr()374 POSTING_READ(FW_BLC_SELF); in _intel_set_memory_cxsr()385 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()388 I915_WRITE(FW_BLC_SELF, val); in _intel_set_memory_cxsr()389 POSTING_READ(FW_BLC_SELF); in _intel_set_memory_cxsr()2449 I915_WRITE(FW_BLC_SELF, in i9xx_update_wm()2452 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()6444 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
2896 #define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */ macro
158 sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; in i915_sr_status()