Searched refs:GICD_ICENABLER (Results 1 – 6 of 6) sorted by relevance
83 GIC_REG_32(GICD_ICENABLER(vector / 32)) = 1U << (vector % 32); /* 32: Interrupt bit width */ in HalIrqMask()139 GIC_REG_32(GICD_ICENABLER(i / 32)) = ~0; /* 32: Interrupt bit width */ in HalIrqInit()
263 GIC_REG_32(GICD_ICENABLER(vector >> 5)) = mask; in HalIrqMask()372 GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff; /* 32: Interrupt bit width */ in HalIrqInit()388 GIC_REG_32(GICD_ICENABLER(i / 32)) = 0xffffffff; /* 32: Interrupt bit width */ in HalIrqInit()
65 #define GICD_ICENABLER(n) (GICD_OFFSET + 0x180 + (n) * 4) /* Interrupt Clear-Enable R… macro
24 #define GICD_ICENABLER 0x0180 macro230 #define GICR_ICENABLER0 GICD_ICENABLER
308 case GICD_ICENABLER: in convert_offset_index()376 gic_poke_irq(d, GICD_ICENABLER); in gic_mask_irq()423 reg = val ? GICD_ICENABLER : GICD_ISENABLER; in gic_irq_set_irqchip_state()
562 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,