Searched refs:GICD_ISPENDR (Results 1 – 7 of 7) sorted by relevance
66 #define GICD_ISPENDR(n) (GICD_OFFSET + 0x200 + (n) * 4) /* Interrupt Set-Pending Re… macro
101 GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32); /* 5, 32: Register bit offset */ in HalIrqPending()
294 …GIC_REG_32(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32); /* 5: Register bit offset, 32: Interr… in HalIrqPending()
25 #define GICD_ISPENDR 0x0200 macro231 #define GICR_ISPENDR0 GICD_ISPENDR
98 following registers: GICD_STATUSR, GICR_STATUSR, GICD_ISPENDR,131 Accesses (reads and writes) to the GICD_ISPENDR register region and
310 case GICD_ISPENDR: in convert_offset_index()415 reg = val ? GICD_ISPENDR : GICD_ICPENDR; in gic_irq_set_irqchip_state()442 *val = gic_peek_irq(d, GICD_ISPENDR); in gic_irq_get_irqchip_state()
566 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,