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Searched refs:HIWORD_UPDATE (Results 1 – 25 of 29) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
Drockchip_lvds.h109 #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) macro
112 #define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8)
113 #define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9)
114 #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)
117 #define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13)
118 #define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12)
119 #define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11)
120 #define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6)
121 #define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1)
Ddw_hdmi-rockchip.c53 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
338 HIWORD_UPDATE(RK3228_HDMI_HPD_VSEL | RK3228_HDMI_SDA_VSEL | in dw_hdmi_rk3228_setup_hpd()
345 HIWORD_UPDATE(RK3228_HDMI_SDAIN_MSK | RK3228_HDMI_SCLIN_MSK, in dw_hdmi_rk3228_setup_hpd()
360 HIWORD_UPDATE(RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V, in dw_hdmi_rk3328_read_hpd()
365 HIWORD_UPDATE(0, RK3328_HDMI_SDA_5V | in dw_hdmi_rk3328_read_hpd()
379 HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V | in dw_hdmi_rk3328_setup_hpd()
384 HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF | in dw_hdmi_rk3328_setup_hpd()
389 HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK, in dw_hdmi_rk3328_setup_hpd()
419 .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL),
420 .lcdsel_lit = HIWORD_UPDATE(RK3288_HDMI_LCDC_SEL, RK3288_HDMI_LCDC_SEL),
[all …]
Ddw-mipi-dsi-rockchip.c175 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
1152 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL),
1153 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL,
1157 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE |
1170 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL),
1171 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL),
1178 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL),
1179 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL),
1190 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL),
1191 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL,
[all …]
Danalogix_dp-rockchip.c39 #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) macro
445 .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
446 .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
452 .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
453 .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
/kernel/linux/linux-5.10/drivers/soc/rockchip/
Dgrf.c14 #define HIWORD_UPDATE(val, mask, shift) \ macro
35 { "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
46 { "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
57 { "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
69 { "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
70 { "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
81 { "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
92 { "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
103 { "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
/kernel/linux/linux-5.10/drivers/phy/rockchip/
Dphy-rockchip-emmc.c23 #define HIWORD_UPDATE(val, mask, shift) \ macro
100 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, in rockchip_emmc_phy_power()
105 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, in rockchip_emmc_phy_power()
158 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, in rockchip_emmc_phy_power()
181 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, in rockchip_emmc_phy_power()
187 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, in rockchip_emmc_phy_power()
282 HIWORD_UPDATE(rk_phy->drive_impedance, in rockchip_emmc_phy_power_on()
289 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, in rockchip_emmc_phy_power_on()
296 HIWORD_UPDATE(4, in rockchip_emmc_phy_power_on()
Dphy-rockchip-pcie.c26 #define HIWORD_UPDATE(val, mask, shift) \ macro
104 HIWORD_UPDATE(data, in phy_wr_cfg()
107 HIWORD_UPDATE(addr, in phy_wr_cfg()
112 HIWORD_UPDATE(PHY_CFG_WR_ENABLE, in phy_wr_cfg()
117 HIWORD_UPDATE(PHY_CFG_WR_DISABLE, in phy_wr_cfg()
128 HIWORD_UPDATE(addr, in phy_rd_cfg()
147 HIWORD_UPDATE(PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
168 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_off()
195 HIWORD_UPDATE(PHY_CFG_PLL_LOCK, in rockchip_pcie_phy_power_on()
201 HIWORD_UPDATE(!PHY_LANE_IDLE_OFF, in rockchip_pcie_phy_power_on()
[all …]
Dphy-rockchip-usb.c28 #define HIWORD_UPDATE(val, mask) \ macro
83 u32 val = HIWORD_UPDATE(siddq ? UOC_CON0_SIDDQ : 0, UOC_CON0_SIDDQ); in rockchip_usb_phy_power()
336 val = HIWORD_UPDATE(UOC_CON0_COMMON_ON_N in rockchip_init_usb_uart_common()
346 val = HIWORD_UPDATE(UOC_CON2_SOFT_CON_SEL, in rockchip_init_usb_uart_common()
352 val = HIWORD_UPDATE(UOC_CON3_UTMI_OPMODE_NODRIVING in rockchip_init_usb_uart_common()
384 val = HIWORD_UPDATE(RK3188_UOC0_CON0_BYPASSSEL in rk3188_init_usb_uart()
434 val = HIWORD_UPDATE(RK3288_UOC0_CON3_BYPASSSEL in rk3288_init_usb_uart()
/kernel/linux/linux-5.10/drivers/clk/rockchip/
Dclk-pll.c214 writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3036_PLLCON0_FBDIV_MASK, in rockchip_rk3036_pll_set_params()
216 HIWORD_UPDATE(rate->postdiv1, RK3036_PLLCON0_POSTDIV1_MASK, in rockchip_rk3036_pll_set_params()
220 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
222 HIWORD_UPDATE(rate->postdiv2, RK3036_PLLCON1_POSTDIV2_MASK, in rockchip_rk3036_pll_set_params()
224 HIWORD_UPDATE(rate->dsmpd, RK3036_PLLCON1_DSMPD_MASK, in rockchip_rk3036_pll_set_params()
272 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), in rockchip_rk3036_pll_enable()
283 writel(HIWORD_UPDATE(RK3036_PLLCON1_PWRDOWN, in rockchip_rk3036_pll_disable()
447 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), in rockchip_rk3066_pll_set_params()
451 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, in rockchip_rk3066_pll_set_params()
453 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, in rockchip_rk3066_pll_set_params()
[all …]
Dclk-cpu.c165 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, in rockchip_cpuclk_pre_rate_change()
167 HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
173 writel(HIWORD_UPDATE(reg_data->mux_core_alt, in rockchip_cpuclk_pre_rate_change()
209 writel(HIWORD_UPDATE(0, reg_data->div_core_mask, in rockchip_cpuclk_post_rate_change()
211 HIWORD_UPDATE(reg_data->mux_core_main, in rockchip_cpuclk_post_rate_change()
Dclk-rk3188.c112 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
118 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
120 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
122 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
124 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
163 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
Dclk-inverter.c49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
Dclk-rk3288.c138 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
140 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
146 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
148 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
150 HIWORD_UPDATE(_pclk_dbg_pre, \
Dclk-mmc-phase.c138 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), in rockchip_mmc_set_phase()
Dclk-rk3036.c86 .val = HIWORD_UPDATE(_core_periph_div, RK3036_DIV_PERI_MASK, \
450 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10), in rk3036_clk_init()
Dclk-rk3368.c186 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
192 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
194 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
Dclk-rk3128.c83 .val = HIWORD_UPDATE(_pclk_dbg_div, RK3128_DIV_PERI_MASK, \
85 HIWORD_UPDATE(_core_aclk_div, RK3128_DIV_ACLK_MASK, \
Dclk-rk3228.c84 .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
86 HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
Dclk-rk3328.c96 .val = HIWORD_UPDATE(_aclk_core, RK3328_DIV_ACLKM_MASK, \
98 HIWORD_UPDATE(_pclk_dbg, RK3328_DIV_PCLK_DBG_MASK, \
Dclk-px30.c81 .val = HIWORD_UPDATE(_aclk_core, PX30_DIV_ACLKM_MASK, \
83 HIWORD_UPDATE(_pclk_dbg, PX30_DIV_PCLK_DBG_MASK, \
Dclk-rk3308.c77 .val = HIWORD_UPDATE(_aclk_core, RK3308_DIV_ACLKM_MASK, \
79 HIWORD_UPDATE(_pclk_dbg, RK3308_DIV_PCLK_DBG_MASK, \
Dclk-rk3399.c323 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
329 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
331 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
/kernel/linux/linux-5.10/drivers/pci/controller/
Dpcie-rockchip.h21 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val)) macro
22 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
32 #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0)
35 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
37 #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
38 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
/kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-rk.c68 #define HIWORD_UPDATE(val, mask, shift) \ macro
144 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
145 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
253 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
254 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
399 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
400 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
491 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
492 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
643 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
[all …]
/kernel/linux/patches/linux-5.10/yangfan_patch/
Ddrivers.patch499 - writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask,
501 - HIWORD_UPDATE(reg_data->mux_core_alt,
507 - writel(HIWORD_UPDATE(reg_data->mux_core_alt,
512 + writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask[i],
521 + writel(HIWORD_UPDATE(reg_data->mux_core_alt,
541 - writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
543 - HIWORD_UPDATE(reg_data->mux_core_main,
547 + writel(HIWORD_UPDATE(reg_data->mux_core_main,
554 + writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
1447 + writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
[all …]

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