Searched refs:I915_MAX_PIPES (Results 1 – 15 of 15) sorted by relevance
25 struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];40 unsigned int data_rate[I915_MAX_PIPES];41 u8 num_active_planes[I915_MAX_PIPES];
43 int min_cdclk[I915_MAX_PIPES];45 u8 min_voltage_level[I915_MAX_PIPES];
303 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
92 I915_MAX_PIPES = _PIPE_EDP enumerator323 for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
457 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init()
1351 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
15369 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_commit_modeset_enables()15406 entries, I915_MAX_PIPES, pipe)) in skl_commit_modeset_enables()15473 entries, I915_MAX_PIPES, pipe)); in skl_commit_modeset_enables()15561 u64 put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()18967 } cursor[I915_MAX_PIPES];18973 } pipe[I915_MAX_PIPES];18983 } plane[I915_MAX_PIPES];
199 int cursor_offsets[I915_MAX_PIPES];222 u8 num_sprites[I915_MAX_PIPES];223 u8 num_scalers[I915_MAX_PIPES];
902 u32 de_irq_mask[I915_MAX_PIPES];904 u32 pipestat_irq_mask[I915_MAX_PIPES];983 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];984 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];1075 u32 chv_dpll_md[I915_MAX_PIPES];1200 struct intel_encoder *av_enc_map[I915_MAX_PIPES];1278 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1304 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument1370 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument1387 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument1411 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument1438 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument1535 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()1620 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()3663 u32 pipe_stats[I915_MAX_PIPES] = {}; in i8xx_irq_handler()3763 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()3906 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
4414 u8 dbuf_mask[I915_MAX_PIPES];
186 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()210 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()341 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()420 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_sprite_plane()
161 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
75 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()570 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { in intel_gvt_check_vblank_emulation()
116 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],