Searched refs:MDREFR (Results 1 – 10 of 10) sorted by relevance
| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 178 sd->mdrefr = MDREFR & 0xffbffff0; in sdram_calculate_timing()
200 MDREFR = (MDREFR & 0xffff000f) | (dri << 4); in sdram_set_refresh()
201 (void) MDREFR; in sdram_set_refresh()
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| /kernel/linux/linux-5.10/arch/arm/mach-sa1100/ |
| D | sleep.S | 36 ldr r6, =MDREFR
124 @ Step 2 clear DRI field in MDREFR
127 @ Step 3 set SLFRSH bit in MDREFR
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | h5000.c | 177 __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR); in fix_msc()
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| D | pxa27x.c | 114 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR); in pxa27x_cpu_pm_save()
122 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR); in pxa27x_cpu_pm_restore()
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| D | reset.c | 86 writel_relaxed(MDREFR_SLFRSH, MDREFR); in do_hw_reset()
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| D | sleep.S | 55 ldr r4, =MDREFR
96 ldr r4, =MDREFR
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
| D | smemc.h | 16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */ macro
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| /kernel/linux/linux-5.10/drivers/clk/pxa/ |
| D | clk-pxa25x.c | 271 pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, MDREFR, CCCR); in clk_pxa25x_cpll_set_rate()
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| D | clk-pxa27x.c | 263 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, MDREFR, CCCR); in clk_pxa27x_cpll_set_rate()
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| /kernel/linux/linux-5.10/arch/arm/mach-sa1100/include/mach/ |
| D | SA-1100.h | 1541 #define MDREFR __REG(0xA000001C) macro
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