/kernel/linux/linux-5.10/arch/arm64/kvm/ |
D | sys_regs.c | 289 switch (p->Op1) { in access_gic_sgi() 349 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, in trap_loregion() 1021 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 1119 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, in read_id_reg() 1154 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, in id_visibility() 1388 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1858 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1860 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1862 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1864 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } [all …]
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D | sys_regs.h | 16 u8 Op1; member 32 u8 Op1; member 75 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_msg() 142 if (i1->Op1 != i2->Op1) in cmp_sys_reg() 143 return i1->Op1 - i2->Op1; in cmp_sys_reg() 157 #define Op1(_x) .Op1 = _x macro 164 Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
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D | trace_handle_exit.h | 165 __field(u8, Op1) 177 __entry->Op1 = reg->Op1; 185 __entry->Op0, __entry->Op1, __entry->CRn,
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/kernel/linux/linux-5.10/arch/arm/include/asm/vdso/ |
D | cp15.h | 14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument 15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32 16 #define __ACCESS_CP15_64(Op1, CRm) \ argument 17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
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/kernel/liteos_a/arch/arm/arm/include/ |
D | los_hw_cpu.h | 85 #define CP14_REG(CRn, Op1, CRm, Op2) "p14, "#Op1", %0, "#CRn","#CRm","#Op2 argument 86 #define CP15_REG(CRn, Op1, CRm, Op2) "p15, "#Op1", %0, "#CRn","#CRm","#Op2 argument 87 #define CP15_REG64(CRn, Op1) "p15, "#Op1", %0, %H0,"#CRn argument
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/kernel/linux/linux-5.10/Documentation/arm64/ |
D | cpu-feature-registers.rst | 95 Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7
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/kernel/linux/linux-5.10/Documentation/virt/kvm/devices/ |
D | arm-vgic-v3.rst | 190 | Op 0 | Op1 | CRn | CRm | Op2 |
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/kernel/linux/patches/linux-5.10/imx8mm_patch/patches/ |
D | 0001_linux_arch.patch | 14274 /* Op1 = 0, CRn = 0, CRm = 6 */ 14279 /* Op1 = 0, CRn = 0, CRm = 7 */
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