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Searched refs:PACKET3_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Dsi_enums.h175 #define PACKET3_CLEAR_STATE 0x12 macro
Dsoc15d.h84 #define PACKET3_CLEAR_STATE 0x12 macro
Dnvd.h59 #define PACKET3_CLEAR_STATE 0x12 macro
Dvid.h116 #define PACKET3_CLEAR_STATE 0x12 macro
Dcikd.h234 #define PACKET3_CLEAR_STATE 0x12 macro
Dsid.h1670 #define PACKET3_CLEAR_STATE 0x12 macro
Dgfx_v6_0.c2072 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start()
2912 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_get_csb_buffer()
Dgfx_v7_0.c2573 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_cp_gfx_start()
4038 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v7_0_get_csb_buffer()
Dgfx_v10_0.c4020 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_get_csb_buffer()
5810 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_cp_gfx_start()
5830 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v10_0_cp_gfx_start()
Dgfx_v8_0.c1286 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
4223 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_cp_gfx_start()
Dgfx_v9_0.c1747 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_get_csb_buffer()
3239 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v9_0_cp_gfx_start()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dnid.h1164 #define PACKET3_CLEAR_STATE 0x12 macro
Dsi.c3606 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3621 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
4541 case PACKET3_CLEAR_STATE: in si_vm_packet3_gfx_check()
4659 case PACKET3_CLEAR_STATE: in si_vm_packet3_compute_check()
5771 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in si_get_csb_buffer()
Dsid.h1607 #define PACKET3_CLEAR_STATE 0x12 macro
Dcikd.h1702 #define PACKET3_CLEAR_STATE 0x12 macro
Devergreen_cs.c1835 case PACKET3_CLEAR_STATE: in evergreen_packet3_check()
3365 case PACKET3_CLEAR_STATE: in evergreen_vm_packet3_check()
Devergreend.h1550 #define PACKET3_CLEAR_STATE 0x12 macro
Dni.c1588 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
Dcik.c4020 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
6771 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_get_csb_buffer()
Devergreen.c3037 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()