| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | rk3188-cru-common.h | 13 #define PLL_CPLL 3 macro
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| D | rk3128-cru.h | 13 #define PLL_CPLL 3 macro
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| D | rk3228-cru.h | 13 #define PLL_CPLL 3 macro
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| D | rk3288-cru.h | 13 #define PLL_CPLL 3 macro
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| D | px30-cru.h | 9 #define PLL_CPLL 3 macro
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| D | rk3328-cru.h | 13 #define PLL_CPLL 3 macro
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| D | rk3368-cru.h | 13 #define PLL_CPLL 4 macro
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| D | rk3399-cru.h | 14 #define PLL_CPLL 4 macro
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-rk3188.c | 218 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
229 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3128.c | 162 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
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| D | clk-rk3228.c | 172 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
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| D | clk-rk3328.c | 220 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rk3368.c | 136 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
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| D | clk-rk3288.c | 229 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
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| D | clk-px30.c | 190 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
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| D | clk-rk3399.c | 225 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/rockchip/ |
| D | rk3368-r88.dts | 211 assigned-clock-parents = <&cru PLL_CPLL>;
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| D | rk3326-odroid-go2.dts | 182 <&cru PLL_CPLL>;
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| D | rk3399-gru-scarlet.dtsi | 321 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| D | rk3399-gru.dtsi | 348 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| D | rk3328.dtsi | 791 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | rk3188-bqedison2qc.dts | 220 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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| D | rk3066a.dtsi | 210 assigned-clocks = <&cru PLL_CPLL>, <&cru PLL_GPLL>,
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| D | rk322x.dtsi | 455 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
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| D | rk3288.dtsi | 887 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
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