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Searched refs:PLL_ENABLE (Results 1 – 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/phy/ti/
Dphy-am654-serdes.c188 PLL_ENABLE, enumerator
229 [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
251 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE); in serdes_am654_enable_pll()
264 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE); in serdes_am654_disable_pll()
/kernel/linux/linux-5.10/drivers/clk/spear/
Dclk-vco-pll.c50 #define PLL_ENABLE 2 macro
315 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
/kernel/linux/linux-5.10/sound/soc/codecs/
Dtlv320aic3x.c1091 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); in aic3x_hw_params()
1097 PLL_ENABLE, PLL_ENABLE); in aic3x_hw_params()
1454 PLL_ENABLE, PLL_ENABLE); in aic3x_set_bias_level()
1464 PLL_ENABLE, 0); in aic3x_set_bias_level()
Dtlv320aic3x.h210 #define PLL_ENABLE 0x80 macro
/kernel/linux/linux-5.10/drivers/clk/tegra/
Dclk-tegra210.c322 #define PLL_ENABLE (1 << 30) macro
734 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
787 if (val & PLL_ENABLE) { in tegra210_plla_set_defaults()
840 PLL_ENABLE) { in tegra210_plld_set_defaults()
893 if (val & PLL_ENABLE) { in plldss_defaults()
1012 if (val & PLL_ENABLE) { in tegra210_pllre_set_defaults()
1137 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1190 if (val & PLL_ENABLE) { in tegra210_pllmb_set_defaults()
1251 if (val & PLL_ENABLE) { in tegra210_pllp_set_defaults()
1314 if (val & PLL_ENABLE) { in tegra210_pllu_set_defaults()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c2351 val |= PLL_ENABLE; in cnl_ddi_pll_enable()
2395 val &= ~PLL_ENABLE; in cnl_ddi_pll_disable()
2439 if (!(val & PLL_ENABLE)) in cnl_ddi_pll_get_hw_state()
3691 if (!(val & PLL_ENABLE)) in mg_pll_get_hw_state()
3755 if (!(val & PLL_ENABLE)) in dkl_pll_get_hw_state()
3829 if (!(val & PLL_ENABLE)) in icl_pll_get_hw_state()
4053 val |= PLL_ENABLE; in icl_pll_enable()
4150 val &= ~PLL_ENABLE; in icl_pll_disable()
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx6q.c384 #define PLL_ENABLE BIT(13) macro
412 reg &= ~PLL_ENABLE; in disable_anatop_clocks()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_reg.h10305 #define PLL_ENABLE (1 << 31) macro