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Searched refs:QM_PEH_AXUSER_CFG (Results 1 – 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/crypto/hisilicon/
Dqm.h49 #define QM_PEH_AXUSER_CFG 0x1000cc macro
/kernel/linux/linux-5.10/drivers/crypto/hisilicon/hpre/
Dhpre_main.c250 val = readl(HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); in disable_flr_of_bme()
253 writel(val, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); in disable_flr_of_bme()
/kernel/linux/linux-5.10/drivers/crypto/hisilicon/zip/
Dzip_main.c268 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG); in hisi_zip_set_user_domain_and_cache()
/kernel/linux/linux-5.10/drivers/crypto/hisilicon/sec2/
Dsec_main.c341 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); in sec_set_user_domain_and_cache()