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Searched refs:R1 (Results 1 – 25 of 152) sorted by relevance

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/kernel/liteos_a/arch/arm/arm/src/
Dlos_hw_runstop.S52 STR R1, [R2, #4]
57 …MOV R1, #72 @This number is the total number of bytes in the task context register(R0~R15, SPS…
58 MUL R1, R1, R0
61 ADD R0, R0, R1
64 MOV R1, SP
65 STMFD R0!, {R1}
67 MRS R1, SPSR
68 STMFD R0!, {R1}
70 MOV R1, LR
71 STMFD R0!, {R1} @PC
[all …]
/kernel/uniproton/src/arch/cpu/armv7-m/cortex-m4/
Dprt_dispatch.S115 LDR R1, [R0]
116 ORR R1, R1,#OS_FLG_BGD_ACTIVE
118 STR R1, [R0]
123 LDR R1, =g_runningTask
124 STR R0, [R1]
127 LDRH R1, [R0, #4]
128 ORR R1, R1, #OS_TSK_RUNNING
129 STRH R1, [R0, #4]
132 LDR R1, [R0]
133 ADD R1, R1, #40
[all …]
Dprt_vector.S77 LDR R1, =g_stackEnd
78 MSR MSP, R1
80 LDR R1, =OS_NVIC_VTOR
81 STR R0, [R1]
86 LDR R1, [R0]
87 ORR R1, #OS_NVIC_UBM_FAULT_ENABLE
88 STR R1, [R0]
93 LDR R1, [R0]
94 ORR R1, #OS_NVIC_UBM_DIV_0_TRP_ENABLE
95 STR R1, [R0]
[all …]
Dprt_hw.S41 LDR R1, [R0]
42 ORR R1, R1, #(0xF << 20)
43 STR R1, [R0]
46 LDR R1, [R0]
47 AND R1, R1, #0XBFFFFFFF
48 ORR R1, R1, #0X80000000
49 STR R1, [R0]
Dprt_hw_exc.S102 MOV R1, #0
110 MOV R1, #HF_DBGEVT
111 LSL R1, R1, #0x8
112 ORR R0, R1
117 MOV R1, #HF_VECTBL
118 LSL R1, R1, #0x8
119 ORR R0, R1
139 LDR R1, =OS_NVIC_BFAR
140 LDR R1, [R1]
145 LDR R1, =OS_NVIC_MMAR
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S34 #define R1 %rbx macro
206 pushq R1
215 movq (R3), R1
217 input_whitening(R1,%r11,a_offset)
221 shr $32, R1
226 encrypt_round(R0,R1,R2,R3,0);
227 encrypt_round(R2,R3,R0,R1,8);
228 encrypt_round(R0,R1,R2,R3,2*8);
229 encrypt_round(R2,R3,R0,R1,3*8);
230 encrypt_round(R0,R1,R2,R3,4*8);
[all …]
Dtwofish-i586-asm_32.S231 encrypt_round(R0,R1,R2,R3,0);
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
239 encrypt_round(R0,R1,R2,R3,8*8);
240 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/secure/
Dlos_secure_context_asm.S46 LDR R1, [R0]
50 BIC R1, R1, R2
53 ORR R1, R1, R2
55 BIC R1, R1, #0x4000
57 ORR R1, R1, R2
58 STR R1, [R0]
68 MRS R1, IPSR
69 CBZ R1, __ThreadMode
71 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
73 MSR PSP, R1 /* Restore PSP. */
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/secure/
Dlos_secure_context_asm.S46 LDR R1, [R0]
50 BIC R1, R1, R2
53 ORR R1, R1, R2
55 BIC R1, R1, #0x4000
57 ORR R1, R1, R2
58 STR R1, [R0]
68 MRS R1, IPSR
69 CBZ R1, __ThreadMode
71 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
73 MSR PSP, R1 /* Restore PSP. */
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/secure/
Dlos_secure_context_asm.S48 LDR R1, [R0]
52 BIC R1, R1, R2
55 ORR R1, R1, R2
57 BIC R1, R1, #0x4000
59 ORR R1, R1, R2
60 STR R1, [R0]
75 MRS R1, IPSR
76 CBZ R1, __ThreadMode
78 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
80 MSR PSP, R1 /* Restore PSP. */
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/secure/
Dlos_secure_context_asm.S48 LDR R1, [R0]
52 BIC R1, R1, R2
55 ORR R1, R1, R2
57 BIC R1, R1, #0x4000
59 ORR R1, R1, R2
60 STR R1, [R0]
75 MRS R1, IPSR
76 CBZ R1, __ThreadMode
78 …LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext…
80 MSR PSP, R1 /* Restore PSP. */
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/
Dlos_dispatch.S53 MOV R1, R0
63 LDR R1, =g_losTask
64 LDR R0, [R1, #4]
67 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
69 STR R1, [R4] /* Set the secureContext to g_secureContext handler. */
73 LDR.W R1, =OS_FPU_CPACR
74 LDR R1, [R1]
75 AND R1, R1, #OS_FPU_CPACR_ENABLE
76 CMP R1, #OS_FPU_CPACR_ENABLE
160 LDR R1, [R2]
[all …]
Dlos_exc.S75 MOV R1, #0
88 MOV R1, #HF_DEBUGEVT
89 ORR R0, R0, R1, LSL #0x8
94 MOV R1, #HF_VECTBL
95 ORR R0, R0, R1, LSL #0x8
120 LDR R1, =OS_NVIC_BFAR
121 LDR R1, [R1]
131 LDR R1, =OS_NVIC_MMAR
132 LDR R1, [R1]
160 LDR R1, =OS_NVIC_BFAR
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/
Dlos_dispatch.S53 MOV R1, R0
63 LDR R1, =g_losTask
64 LDR R0, [R1, #4]
67 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
69 STR R1, [R4] /* Set the secureContext to g_secureContext handler. */
73 LDR.W R1, =OS_FPU_CPACR
74 LDR R1, [R1]
75 AND R1, R1, #OS_FPU_CPACR_ENABLE
76 CMP R1, #OS_FPU_CPACR_ENABLE
160 LDR R1, [R2]
[all …]
Dlos_exc.S75 MOV R1, #0
88 MOV R1, #HF_DEBUGEVT
89 ORR R0, R0, R1, LSL #0x8
94 MOV R1, #HF_VECTBL
95 ORR R0, R0, R1, LSL #0x8
120 LDR R1, =OS_NVIC_BFAR
121 LDR R1, [R1]
131 LDR R1, =OS_NVIC_MMAR
132 LDR R1, [R1]
160 LDR R1, =OS_NVIC_BFAR
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/
Dlos_dispatch.S70 MOV R1, R0
78 LDR R1, =g_losTask
79 LDR R0, [R1, #4]
82 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
84 STR R1, [R4] /* Set the secureContext to g_secureContext handler. */
88 LDR.W R1, =OS_FPU_CPACR
89 LDR R1, [R1]
90 AND R1, R1, #OS_FPU_CPACR_ENABLE
91 CMP R1, #OS_FPU_CPACR_ENABLE
119 LDR R1, =OS_NVIC_PENDSVSET
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/
Dlos_dispatch.S70 MOV R1, R0
78 LDR R1, =g_losTask
79 LDR R0, [R1, #4]
82 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
84 STR R1, [R4] /* Set the secureContext to g_secureContext handler. */
88 LDR.W R1, =OS_FPU_CPACR
89 LDR R1, [R1]
90 AND R1, R1, #OS_FPU_CPACR_ENABLE
91 CMP R1, #OS_FPU_CPACR_ENABLE
119 LDR R1, =OS_NVIC_PENDSVSET
[all …]
/kernel/linux/linux-5.10/lib/
Dtest_bpf.c40 #define R1 BPF_REG_1 macro
1109 BPF_ALU64_IMM(BPF_MOV, R1, 1),
1110 BPF_ALU64_IMM(BPF_ADD, R1, 2),
1112 BPF_ALU64_REG(BPF_SUB, R1, R2),
1113 BPF_ALU64_IMM(BPF_ADD, R1, -1),
1114 BPF_ALU64_IMM(BPF_MUL, R1, 3),
1115 BPF_ALU64_REG(BPF_MOV, R0, R1),
1126 BPF_ALU64_IMM(BPF_MOV, R1, -1),
1128 BPF_ALU64_REG(BPF_MUL, R1, R2),
1129 BPF_JMP_IMM(BPF_JEQ, R1, 0xfffffffd, 1),
[all …]
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
Dlos_exc.S76 MOV R1, #0
89 MOV R1, #HF_DEBUGEVT
90 ORR R0, R0, R1, LSL #0x8
95 MOV R1, #HF_VECTBL
96 ORR R0, R0, R1, LSL #0x8
121 LDR R1, =OS_NVIC_BFAR
122 LDR R1, [R1]
132 LDR R1, =OS_NVIC_MMAR
133 LDR R1, [R1]
158 MRSEQ R1, MSP
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/
Dlos_exc.S69 MOV R1, #0
77 MOV R1, #HF_DEBUGEVT
78 ORR R0, R0, R1, LSL #0x8
83 MOV R1, #HF_VECTBL
84 ORR R0, R0, R1, LSL #0x8
104 LDR R1, =OS_NVIC_BFAR
105 LDR R1, [R1]
110 LDR R1, =OS_NVIC_MMAR
111 LDR R1, [R1]
128 LDR R1, [R0,#24]
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/
Dlos_exc.S69 MOV R1, #0
77 MOV R1, #HF_DEBUGEVT
78 ORR R0, R0, R1, LSL #0x8
83 MOV R1, #HF_VECTBL
84 ORR R0, R0, R1, LSL #0x8
104 LDR R1, =OS_NVIC_BFAR
105 LDR R1, [R1]
110 LDR R1, =OS_NVIC_MMAR
111 LDR R1, [R1]
128 LDR R1, [R0,#24]
[all …]
/kernel/liteos_m/arch/arm/cortex-m7/iar/
Dlos_exc.S69 MOV R1, #0
77 MOV R1, #HF_DEBUGEVT
78 ORR R0, R0, R1, LSL #0x8
83 MOV R1, #HF_VECTBL
84 ORR R0, R0, R1, LSL #0x8
104 LDR R1, =OS_NVIC_BFAR
105 LDR R1, [R1]
110 LDR R1, =OS_NVIC_MMAR
111 LDR R1, [R1]
128 LDR R1, [R0,#24]
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/
Dlos_exc.S73 MOV R1, #0
86 MOV R1, #HF_DEBUGEVT
87 ORR R0, R0, R1, LSL #0x8
92 MOV R1, #HF_VECTBL
93 ORR R0, R0, R1, LSL #0x8
118 LDR R1, =OS_NVIC_BFAR
119 LDR R1, [R1]
129 LDR R1, =OS_NVIC_MMAR
130 LDR R1, [R1]
157 LDR R1, [R0,#24]
[all …]
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
Dlos_exc.S76 MOV R1, #0
89 MOV R1, #HF_DEBUGEVT
90 ORR R0, R0, R1, LSL #0x8
95 MOV R1, #HF_VECTBL
96 ORR R0, R0, R1, LSL #0x8
121 LDR R1, =OS_NVIC_BFAR
122 LDR R1, [R1]
132 LDR R1, =OS_NVIC_MMAR
133 LDR R1, [R1]
160 LDR R1, [R0,#24]
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/
Dlos_exc.S76 MOV R1, #0
89 MOV R1, #HF_DEBUGEVT
90 ORR R0, R0, R1, LSL #0x8
95 MOV R1, #HF_VECTBL
96 ORR R0, R0, R1, LSL #0x8
121 LDR R1, =OS_NVIC_BFAR
122 LDR R1, [R1]
132 LDR R1, =OS_NVIC_MMAR
133 LDR R1, [R1]
160 LDR R1, [R0,#24]
[all …]

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