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Searched refs:R3 (Results 1 – 25 of 97) sorted by relevance

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/kernel/linux/linux-5.10/arch/x86/crypto/
Dtwofish-x86_64-asm_64.S44 #define R3 %rdx macro
215 movq (R3), R1
216 movq 8(R3), R3
218 input_whitening(R3,%r11,c_offset)
223 shr $32, R3
226 encrypt_round(R0,R1,R2,R3,0);
227 encrypt_round(R2,R3,R0,R1,8);
228 encrypt_round(R0,R1,R2,R3,2*8);
229 encrypt_round(R2,R3,R0,R1,3*8);
230 encrypt_round(R0,R1,R2,R3,4*8);
[all …]
Dtwofish-i586-asm_32.S231 encrypt_round(R0,R1,R2,R3,0);
232 encrypt_round(R2,R3,R0,R1,8);
233 encrypt_round(R0,R1,R2,R3,2*8);
234 encrypt_round(R2,R3,R0,R1,3*8);
235 encrypt_round(R0,R1,R2,R3,4*8);
236 encrypt_round(R2,R3,R0,R1,5*8);
237 encrypt_round(R0,R1,R2,R3,6*8);
238 encrypt_round(R2,R3,R0,R1,7*8);
239 encrypt_round(R0,R1,R2,R3,8*8);
240 encrypt_round(R2,R3,R0,R1,9*8);
[all …]
/kernel/linux/linux-5.10/arch/powerpc/lib/
Dhweight_64.S21 PPC_POPCNTB(R3,R3)
36 PPC_POPCNTB(R3,R3)
43 PPC_POPCNTW(R3,R3)
61 PPC_POPCNTB(R3,R3)
69 PPC_POPCNTW(R3,R3)
89 PPC_POPCNTB(R3,R3)
99 PPC_POPCNTD(R3,R3)
/kernel/uniproton/src/arch/cpu/armv7-m/cortex-m4/
Dprt_hw_exc.S47 OS_NORMAL_PUSH_SP_AUTO = 32 @auto save 8 normal R registers(xPSR, PC, LR, R12,R0~R3),8*4
150 LDR R3, =OS_BMU_FAULT_CLEAR_BIT
151 AND R2, R3
153 LDR R3, =excTbl
154 ADD R3, R3, R2
155 LDRB R2, [R3]
210 LDR R3, =OS_BMU_FAULT_CLEAR_BIT
211 AND R0, R3
213 LDR R3, =excTbl
214 ADD R3, R3, R0
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/
Dlos_dispatch.S67 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
86 BX R3
165 POP {R0-R3}
166 MOV LR, R3
171 LDR.W R3, =OS_FPU_CPACR
172 LDR R3, [R3]
173 AND R3, R3, #OS_FPU_CPACR_ENABLE
174 CMP R3, #OS_FPU_CPACR_ENABLE
184 MOV R3, LR
185 …STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of …
[all …]
Dlos_exc.S142 LDR R3, =g_uwExcTbl
143 ADD R3, R3, R2
144 LDRB R2, [R3]
225 LDR R3, =g_uwExcTbl
226 ADD R3, R3, R0
227 LDRB R0, [R3]
246 LDR R3, [R2] // R3 store active hwi register when exc
247 CMP R3, #0
252 RBIT R2, R3
265 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/
Dlos_dispatch.S67 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
86 BX R3
165 POP {R0-R3}
166 MOV LR, R3
171 LDR.W R3, =OS_FPU_CPACR
172 LDR R3, [R3]
173 AND R3, R3, #OS_FPU_CPACR_ENABLE
174 CMP R3, #OS_FPU_CPACR_ENABLE
184 MOV R3, LR
185 …STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of …
[all …]
Dlos_exc.S142 LDR R3, =g_uwExcTbl
143 ADD R3, R3, R2
144 LDRB R2, [R3]
225 LDR R3, =g_uwExcTbl
226 ADD R3, R3, R0
227 LDRB R0, [R3]
246 LDR R3, [R2] // R3 store active hwi register when exc
247 CMP R3, #0
252 RBIT R2, R3
265 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/
Dlos_exc.S115 LDR R3, =g_uwExcTbl
116 ADD R3, R3, R2
117 LDRB R2, [R3]
167 LDR R3, =g_uwExcTbl
168 ADD R3, R3, R0
169 LDRB R0, [R3]
178 LDR R3, [R2] ; R3 store active hwi register when exc
179 CMP R3, #0
184 RBIT R2, R3
192 ADD R3, R13, #104
[all …]
Dlos_dispatch.S82 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
101 BX R3
151 POP {R0-R3}
152 MOV LR, R3
157 LDR.W R3, =OS_FPU_CPACR
158 LDR R3, [R3]
159 AND R3, R3, #OS_FPU_CPACR_ENABLE
160 CMP R3, #OS_FPU_CPACR_ENABLE
170 MOV R3, LR
171 …STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of …
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/
Dlos_exc.S116 LDR R3, =g_uwExcTbl
117 ADD R3, R3, R2
118 LDRB R2, [R3]
178 LDR R3, =g_uwExcTbl
179 ADD R3, R3, R0
180 LDRB R0, [R3]
189 LDR R3, [R2] ; R3 store active hwi register when exc
190 CMP R3, #0
195 RBIT R2, R3
203 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/
Dlos_exc.S116 LDR R3, =g_uwExcTbl
117 ADD R3, R3, R2
118 LDRB R2, [R3]
178 LDR R3, =g_uwExcTbl
179 ADD R3, R3, R0
180 LDRB R0, [R3]
189 LDR R3, [R2] ; R3 store active hwi register when exc
190 CMP R3, #0
195 RBIT R2, R3
203 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/
Dlos_exc.S115 LDR R3, =g_uwExcTbl
116 ADD R3, R3, R2
117 LDRB R2, [R3]
167 LDR R3, =g_uwExcTbl
168 ADD R3, R3, R0
169 LDRB R0, [R3]
178 LDR R3, [R2] ; R3 store active hwi register when exc
179 CMP R3, #0
184 RBIT R2, R3
192 ADD R3, R13, #104
[all …]
Dlos_dispatch.S82 …LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 =…
101 BX R3
151 POP {R0-R3}
152 MOV LR, R3
157 LDR.W R3, =OS_FPU_CPACR
158 LDR R3, [R3]
159 AND R3, R3, #OS_FPU_CPACR_ENABLE
160 CMP R3, #OS_FPU_CPACR_ENABLE
170 MOV R3, LR
171 …STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of …
[all …]
/kernel/liteos_m/arch/arm/cortex-m7/iar/
Dlos_exc.S116 LDR R3, =g_uwExcTbl
117 ADD R3, R3, R2
118 LDRB R2, [R3]
178 LDR R3, =g_uwExcTbl
179 ADD R3, R3, R0
180 LDRB R0, [R3]
189 LDR R3, [R2] ; R3 store active hwi register when exc
190 CMP R3, #0
195 RBIT R2, R3
203 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
Dlos_exc.S143 LDR R3, =g_uwExcTbl
144 ADD R3, R3, R2
145 LDRB R2, [R3]
256 LDR R3, =g_uwExcTbl
257 ADD R3, R3, R0
258 LDRB R0, [R3]
277 LDR R3, [R2] // R3 store active hwi register when exc
278 CMP R3, #0
283 RBIT R2, R3
296 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/
Dlos_exc.S140 LDR R3, =g_uwExcTbl
141 ADD R3, R3, R2
142 LDRB R2, [R3]
238 LDR R3, =g_uwExcTbl
239 ADD R3, R3, R0
240 LDRB R0, [R3]
259 LDR R3, [R2] // R3 store active hwi register when exc
260 CMP R3, #0
265 RBIT R2, R3
278 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
Dlos_exc.S143 LDR R3, =g_uwExcTbl
144 ADD R3, R3, R2
145 LDRB R2, [R3]
241 LDR R3, =g_uwExcTbl
242 ADD R3, R3, R0
243 LDRB R0, [R3]
262 LDR R3, [R2] // R3 store active hwi register when exc
263 CMP R3, #0
268 RBIT R2, R3
281 ADD R3, R13, #104
[all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/
Dlos_exc.S143 LDR R3, =g_uwExcTbl
144 ADD R3, R3, R2
145 LDRB R2, [R3]
241 LDR R3, =g_uwExcTbl
242 ADD R3, R3, R0
243 LDRB R0, [R3]
262 LDR R3, [R2] // R3 store active hwi register when exc
263 CMP R3, #0
268 RBIT R2, R3
281 ADD R3, R13, #104
[all …]
/kernel/liteos_a/arch/arm/arm/src/
Dlos_hw_exc.S104 MOV R3, LR @save pc
115 STR R3, [R0, #8] @PC
164 MOV R3, R0
165 ORR R2, R3, #0X80000000
178 STMFD SP!, {R0-R3, R12, LR}
182 MOV R3, #0
183 …STMFD SP!, {R2-R3} @ far and fsr fields, are 0 under this a…
193 STMFD SP!, {R0-R3, R12, LR}
199 LDR R3, [SP, #(11 * 4)]
200 AND R1, R3, #CPSR_MASK_MODE @ Interrupted mode
[all …]
Dlos_dispatch.S117 LDR R3, [SP, #(11 * 4)]
118 AND R0, R3, #CPSR_MASK_MODE
123 AND R3, R3, R2
124 STR R3, [SP, #(11 * 4)]
134 LDMFD SP!, {R0-R3, R12, LR}
139 LDMFD SP!, {R0-R3, R12, LR}
151 PUSH {R0-R3, R12, LR}
155 POP {R0-R3, R12, LR}
158 STMFD SP!, {R0-R3, R12, LR}
186 LDR R3, [SP, #(11 * 4)]
[all …]
/kernel/liteos_m/arch/arm/cortex-m4/iar/
Dlos_exc.S116 LDR R3, =g_uwExcTbl
117 ADD R3, R3, R2
118 LDRB R2, [R3]
178 LDR R3, =g_uwExcTbl
179 ADD R3, R3, R0
180 LDRB R0, [R3]
189 LDR R3, [R2] ; R3 store active hwi register when exc
190 CMP R3, #0
195 RBIT R2, R3
203 ADD R3, R13, #104
[all …]
Dlos_dispatch.S146 LDR.W R3, =OS_FPU_CPACR
147 LDR R3, [R3]
148 AND R3, R3, #OS_FPU_CPACR_ENABLE
149 CMP R3, #OS_FPU_CPACR_ENABLE
163 LDR.W R3, =OS_FPU_CPACR
164 LDR R3, [R3]
165 AND R3, R3, #OS_FPU_CPACR_ENABLE
166 CMP R3, #OS_FPU_CPACR_ENABLE
/kernel/liteos_m/arch/arm/cortex-m3/keil/
Dlos_exc.S116 LDR R3, =g_uwExcTbl
117 ADD R3, R3, R2
118 LDRB R2, [R3]
178 LDR R3, =g_uwExcTbl
179 ADD R3, R3, R0
180 LDRB R0, [R3]
189 LDR R3, [R2] ; R3 store active hwi register when exc
190 CMP R3, #0
195 RBIT R2, R3
203 ADD R3, R13, #104
[all …]
/kernel/linux/linux-5.10/arch/arm/crypto/
Dpoly1305-armv4.pl495 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("d$_",(0..9));
538 vdup.32 $R3,r5
557 vmull.u32 $D3,$R3,${R0}[1]
564 vmlal.u32 $D4,$R3,${R1}[1]
566 vmlal.u32 $D0,$R3,${S2}[1]
573 vmlal.u32 $D3,$R0,${R3}[1]
574 vmlal.u32 $D1,$R3,${S3}[1]
576 vmlal.u32 $D4,$R1,${R3}[1]
581 vmlal.u32 $D2,$R3,${S4}[1]
609 @ H4 = H4*R0 + H3*R1 + H2*R2 + H1*R3 + H0 * R4,
[all …]

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