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Searched refs:REG_FIELD_PREP (Results 1 – 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_lvds.c214 …REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps-… in intel_lvds_pps_init_hw()
217 …REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, … in intel_lvds_pps_init_hw()
220 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_M… in intel_lvds_pps_init_hw()
Dintel_dp.c7132 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in intel_dp_init_panel_power_sequencer_registers()
7133 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in intel_dp_init_panel_power_sequencer_registers()
7134 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in intel_dp_init_panel_power_sequencer_registers()
7135 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in intel_dp_init_panel_power_sequencer_registers()
7168 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_… in intel_dp_init_panel_power_sequencer_registers()
7174 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); in intel_dp_init_panel_power_sequencer_registers()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
Di915_reg.h162 #define REG_FIELD_PREP(__mask, __val) \ macro
2085 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MAS…
3244 #define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
3249 #define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
3251 #define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
4399 #define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
4400 #define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
4401 #define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
4402 #define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
4403 #define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.c140 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); in gen11_enable_guc_interrupts()