Searched refs:SEV (Results 1 – 9 of 9) sorted by relevance
2 Secure Encrypted Virtualization (SEV)8 Secure Encrypted Virtualization (SEV) is a feature found on AMD processors.10 SEV is an extension to the AMD-V architecture which supports running15 The hypervisor can determine the SEV support through the CPUID17 to SEV::20 Bit[1] indicates support for SEV25 If support for SEV is present, MSR 0xc001_0010 (MSR_K8_SYSCFG) and MSR 0xc001_001536 When SEV support is available, it can be enabled in a specific VM by37 setting the SEV bit before executing VMRUN.::40 Bit[1] 1 = SEV is enabled[all …]
4229 (SEV) commands on AMD Processors. The SEV commands are defined in4244 It is used in the SEV-enabled guest. When encryption is enabled, a guest4245 memory region may contain encrypted data. The SEV memory encryption4249 swapped. So relocating (or migrating) physical backing pages for the SEV4252 Note: The current SEV key management spec does not provide commands to
7 Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are16 SEV enables running encrypted virtual machines (VMs) in which the code and data18 within the VM itself. SEV guest VMs have the concept of private and shared36 When SEV is enabled, instruction pages and guest page tables are always treated39 is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware42 Support for SME and SEV can be determined through the CPUID instruction. The47 Bit[1] indicates support for SEV63 If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if64 SEV is active::
39 #define SEV __ALT_SMP_ASM(WASM(sev), WASM(nop)) macro45 __asm__(SEV); in dsb_sev()
87 SEV; in HalSecondaryCpuStart()
45 management commands in Secure Encrypted Virtualization (SEV) mode,
57 #define SEV __asm__ volatile("sev" ::: "memory") macro
99 bool "AMD Secure Encrypted Virtualization (SEV) support"
846 AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - SEV SUPPORT