1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef KFD_DBGDEV_H_ 24 #define KFD_DBGDEV_H_ 25 26 enum { 27 SQ_CMD_VMID_OFFSET = 28, 28 ADDRESS_WATCH_CNTL_OFFSET = 24 29 }; 30 31 enum { 32 PRIV_QUEUE_SYNC_TIME_MS = 200 33 }; 34 35 /* CONTEXT reg space definition */ 36 enum { 37 CONTEXT_REG_BASE = 0xA000, 38 CONTEXT_REG_END = 0xA400, 39 CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE 40 }; 41 42 /* USER CONFIG reg space definition */ 43 enum { 44 USERCONFIG_REG_BASE = 0xC000, 45 USERCONFIG_REG_END = 0x10000, 46 USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE 47 }; 48 49 /* CONFIG reg space definition */ 50 enum { 51 AMD_CONFIG_REG_BASE = 0x2000, /* in dwords */ 52 AMD_CONFIG_REG_END = 0x2B00, 53 AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE 54 }; 55 56 /* SH reg space definition */ 57 enum { 58 SH_REG_BASE = 0x2C00, 59 SH_REG_END = 0x3000, 60 SH_REG_SIZE = SH_REG_END - SH_REG_BASE 61 }; 62 63 /* SQ_CMD definitions */ 64 #define SQ_CMD 0x8DEC 65 66 enum SQ_IND_CMD_CMD { 67 SQ_IND_CMD_CMD_NULL = 0x00000000, 68 SQ_IND_CMD_CMD_HALT = 0x00000001, 69 SQ_IND_CMD_CMD_RESUME = 0x00000002, 70 SQ_IND_CMD_CMD_KILL = 0x00000003, 71 SQ_IND_CMD_CMD_DEBUG = 0x00000004, 72 SQ_IND_CMD_CMD_TRAP = 0x00000005, 73 }; 74 75 enum SQ_IND_CMD_MODE { 76 SQ_IND_CMD_MODE_SINGLE = 0x00000000, 77 SQ_IND_CMD_MODE_BROADCAST = 0x00000001, 78 SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002, 79 SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003, 80 SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004, 81 }; 82 83 union SQ_IND_INDEX_BITS { 84 struct { 85 uint32_t wave_id:4; 86 uint32_t simd_id:2; 87 uint32_t thread_id:6; 88 uint32_t:1; 89 uint32_t force_read:1; 90 uint32_t read_timeout:1; 91 uint32_t unindexed:1; 92 uint32_t index:16; 93 94 } bitfields, bits; 95 uint32_t u32All; 96 signed int i32All; 97 float f32All; 98 }; 99 100 union SQ_IND_CMD_BITS { 101 struct { 102 uint32_t data:32; 103 } bitfields, bits; 104 uint32_t u32All; 105 signed int i32All; 106 float f32All; 107 }; 108 109 union SQ_CMD_BITS { 110 struct { 111 uint32_t cmd:3; 112 uint32_t:1; 113 uint32_t mode:3; 114 uint32_t check_vmid:1; 115 uint32_t trap_id:3; 116 uint32_t:5; 117 uint32_t wave_id:4; 118 uint32_t simd_id:2; 119 uint32_t:2; 120 uint32_t queue_id:3; 121 uint32_t:1; 122 uint32_t vm_id:4; 123 } bitfields, bits; 124 uint32_t u32All; 125 signed int i32All; 126 float f32All; 127 }; 128 129 union SQ_IND_DATA_BITS { 130 struct { 131 uint32_t data:32; 132 } bitfields, bits; 133 uint32_t u32All; 134 signed int i32All; 135 float f32All; 136 }; 137 138 union GRBM_GFX_INDEX_BITS { 139 struct { 140 uint32_t instance_index:8; 141 uint32_t sh_index:8; 142 uint32_t se_index:8; 143 uint32_t:5; 144 uint32_t sh_broadcast_writes:1; 145 uint32_t instance_broadcast_writes:1; 146 uint32_t se_broadcast_writes:1; 147 } bitfields, bits; 148 uint32_t u32All; 149 signed int i32All; 150 float f32All; 151 }; 152 153 union TCP_WATCH_ADDR_H_BITS { 154 struct { 155 uint32_t addr:16; 156 uint32_t:16; 157 158 } bitfields, bits; 159 uint32_t u32All; 160 signed int i32All; 161 float f32All; 162 }; 163 164 union TCP_WATCH_ADDR_L_BITS { 165 struct { 166 uint32_t:6; 167 uint32_t addr:26; 168 } bitfields, bits; 169 uint32_t u32All; 170 signed int i32All; 171 float f32All; 172 }; 173 174 enum { 175 QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */ 176 QUEUESTATE__ACTIVE_COMPLETION_PENDING, 177 QUEUESTATE__ACTIVE 178 }; 179 180 union ULARGE_INTEGER { 181 struct { 182 uint32_t low_part; 183 uint32_t high_part; 184 } u; 185 unsigned long long quad_part; 186 }; 187 188 189 #define KFD_CIK_VMID_START_OFFSET (8) 190 #define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8)) 191 192 193 void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev, 194 enum DBGDEV_TYPE type); 195 196 union TCP_WATCH_CNTL_BITS { 197 struct { 198 uint32_t mask:24; 199 uint32_t vmid:4; 200 uint32_t atc:1; 201 uint32_t mode:2; 202 uint32_t valid:1; 203 } bitfields, bits; 204 uint32_t u32All; 205 signed int i32All; 206 float f32All; 207 }; 208 209 enum { 210 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, 211 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, 212 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, 213 /* extend the mask to 26 bits in order to match the low address field */ 214 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, 215 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF 216 }; 217 218 enum { 219 MAX_TRAPID = 8, /* 3 bits in the bitfield. */ 220 MAX_WATCH_ADDRESSES = 4 221 }; 222 223 enum { 224 ADDRESS_WATCH_REG_ADDR_HI = 0, 225 ADDRESS_WATCH_REG_ADDR_LO, 226 ADDRESS_WATCH_REG_CNTL, 227 ADDRESS_WATCH_REG_MAX 228 }; 229 230 #endif /* KFD_DBGDEV_H_ */ 231