Searched refs:SSPP_DMA0 (Results 1 – 8 of 8) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/ |
D | mdp5_cfg.c | 29 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 113 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 197 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 290 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4, 357 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4, 434 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13, 642 [SSPP_DMA0] = 4,
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D | mdp5_ctl.c | 296 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage); in mdp_ctl_blend_mask() 319 case SSPP_DMA0: return MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3; in mdp_ctl_blend_ext_mask() 447 case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0; in mdp_ctl_flush_mask_pipe()
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D | mdp5.xml.h | 75 SSPP_DMA0 = 7, enumerator 545 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]); in __offset_PIPE()
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D | mdp5_kms.c | 730 SSPP_DMA0, SSPP_DMA1, in hwpipe_init() enumerator
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
D | dpu_hw_top.c | 146 status->sspp[SSPP_DMA0] = (value >> 20) & 0x3; in dpu_hw_get_danger_status() 243 status->sspp[SSPP_DMA0] = (value >> 20) & 0x1; in dpu_hw_get_safe_status()
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D | dpu_hw_ctl.c | 165 case SSPP_DMA0: in dpu_hw_ctl_get_bitmask_sspp() 435 case SSPP_DMA0: in dpu_hw_ctl_setup_blendstage()
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D | dpu_hw_mdss.h | 117 SSPP_DMA0, enumerator
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D | dpu_hw_catalog.c | 350 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 366 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
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